Inventor · disambiguated record
Wai Hung William Hor
Also filed as: HOR WAI HUNG · HOR WAI HUNG WILLIAM
3 granted patents·6 pending applications·15 citations·filing 2014–2025
64Inventor score
Top patents by PatentIndex Score
9 records- 0183US9443791B2Leadless semiconductor package and methodNXP BV·Filed 2015·Granted Sep 13, 2016·7 cites·15 claims
- 0277US9425130B2Package with multiple I/O side-solderable terminalsNXP BV·Filed 2014·Granted Aug 23, 2016·7 cites·13 claims
- 0375US11227820B2Through hole side wettable flankNexperia BV·Filed 2020·Granted Jan 18, 2022·1 cites·20 claims
- 0459US2025174526A1Semiconductor packageNexperia BV·Filed 2024·Application pending·0 cites
- 0556US2025006597A1Semiconductor device as well as a method for manufacturing such semiconductor deviceNexperia BV·Filed 2024·Application pending·0 cites
- 0652US2024105514A1Method of singulation of dies from a waferNexperia BV·Filed 2023·Application pending·0 cites
- 0752US2025385193A1A leadless package comprising a first and a second semiconductor die, wherein a galvanic coupling is provided between those semiconductor dies, as well as a corresponding methodNexperia BV·Filed 2025·Application pending·0 cites
- 0850US2023178507A1Step interconnect metallization to enable panel level packagingNexperia BV·Filed 2022·Application pending·0 cites
- 0930US2018151482A1Electronic device, manufacturing method and lead frame for sameNexperia BV·Filed 2016·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →