Inventor · disambiguated record
Wan L. Leung
Also filed as: LEUNG WAN L · LEUNG WAN LIN
13 granted patents·530 citations·filing 1984–1998
94Inventor score
Technology areasG06F
Files withIBM13
Top patents by PatentIndex Score
13 records- 0184US5003465AMethod and apparatus for increasing system throughput via an input/output bus and enhancing address capability of a computer system during DMA read/write operations between a common memory and an input/output deviceIBM·Filed 1988·Granted Mar 26, 1991·90 cites·27 claims
- 0279US5900017ASnooping a variable number of cache addresses in a multiple processor system by a single snoop requestIBM·Filed 1997·Granted May 4, 1999·80 cites·4 claims
- 0375US4695950AFast two-level dynamic address translation method and meansIBM·Filed 1984·Granted Sep 22, 1987·51 cites·10 claims
- 0465US6009509AMethod and system for the temporary designation and utilization of a plurality of physical registers as a stackIBM·Filed 1997·Granted Dec 28, 1999·49 cites·14 claims
- 0562US5664150AComputer system with a device for selectively blocking writebacks of data from a writeback cache to memoryIBM·Filed 1995·Granted Sep 2, 1997·47 cites·16 claims
- 0662US5598542AMethod and apparatus for bus arbitration in a multiple bus information handling system using time slot assignment valuesIBM·Filed 1994·Granted Jan 28, 1997·38 cites·14 claims
- 0760US5893148ASystem and method for allocating cache memory storage spaceIBM·Filed 1997·Granted Apr 6, 1999·40 cites·21 claims
- 0852US6338134B1Method and system in a superscalar data processing system for the efficient processing of an instruction by moving only pointers to dataIBM·Filed 1998·Granted Jan 8, 2002·30 cites·46 claims
- 0952US6003126ASpecial instruction register including allocation field utilized for temporary designation of physical registers as general registersIBM·Filed 1997·Granted Dec 14, 1999·32 cites·8 claims
- 1051US6151661ACache memory storage space management system and methodIBM·Filed 1994·Granted Nov 21, 2000·26 cites·5 claims
- 1147US5923898ASystem for executing I/O request when an I/O request queue entry matches a snoop table entry or executing snoop when not matchedIBM·Filed 1997·Granted Jul 13, 1999·21 cites·12 claims
- 1245US5293491AData processing system and memory controller for lock semaphore operationsIBM·Filed 1990·Granted Mar 8, 1994·22 cites·10 claims
- 1332US6260118B1Snooping a variable number of cache addresses in a multiple processor system by a single snoop requestIBM·Filed 1998·Granted Jul 10, 2001·4 cites·6 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →