Inventor · disambiguated record
Wayne A. Michaelson
Also filed as: MICHAELSON WAYNE A · MICHAELSON WAYNE ALAN
24 granted patents·970 citations·filing 1984–1995
97Inventor score
Top patents by PatentIndex Score
24 records- 0194US5060145AMemory access system for pipelined data paths to and from storageUNISYS CORP·Filed 1989·Granted Oct 22, 1991·89 cites·17 claims
- 0293US5487159ASystem for processing shift, mask, and merge operations in one instructionUNISYS CORP·Filed 1993·Granted Jan 23, 1996·197 cites·4 claims
- 0391US4600986APipelined split stack with high performance interleaved decodeSPERRY CORP·Filed 1984·Granted Jul 15, 1986·108 cites·13 claims
- 0489US5488702AData block check sequence generation and validation in a file cache systemUNISYS CORP·Filed 1994·Granted Jan 30, 1996·147 cites·20 claims
- 0579US4674032AHigh-performance pipelined stack with over-write protectionUNISYS CORP·Filed 1984·Granted Jun 16, 1987·54 cites·5 claims
- 0677US5555391ASystem and method for storing partial blocks of file data in a file cache system by merging partial updated blocks with file block to be writtenUNISYS CORP·Filed 1993·Granted Sep 10, 1996·82 cites·13 claims
- 0776US5535405AMicrosequencer bus controller systemUNISYS CORP·Filed 1993·Granted Jul 9, 1996·71 cites·32 claims
- 0862US5471597ASystem and method for executing branch instructions wherein branch target addresses are dynamically selectable under programmer control from writable branch address tablesUNISYS CORP·Filed 1994·Granted Nov 28, 1995·40 cites·2 claims
- 0952US5612965AMultiple memory bit/chip failure detectionUNISYS CORP·Filed 1995·Granted Mar 18, 1997·26 cites·20 claims
- 1050US5453999AAddress verification system using parity for transmitting and receiving circuitsUNISYS CORP·Filed 1994·Granted Sep 26, 1995·29 cites·15 claims
- 1150US4590586AForced clear of a memory time-out to a maintenance exerciserSPERRY CORP·Filed 1984·Granted May 20, 1986·18 cites·3 claims
- 1248US5440604ACounter malfunction detection using prior, current and predicted parityUNISYS CORP·Filed 1994·Granted Aug 8, 1995·20 cites·11 claims
- 1341US5539888ASystem and method for processing external conditional branch instructionsUNISYS CORP·Filed 1995·Granted Jul 23, 1996·14 cites·2 claims
- 1441US5495598AStuck fault detection for branch instruction condition signalsUNISYS CORP·Filed 1993·Granted Feb 27, 1996·13 cites·6 claims
- 1539US4933908AFault detection in memory refreshing systemUNISYS CORP·Filed 1988·Granted Jun 12, 1990·6 cites·7 claims
- 1639US4926313ABifurcated register priority systemUNISYS CORP·Filed 1988·Granted May 15, 1990·10 cites·9 claims
- 1737US5515507AMultiple width data bus for a microsequencer bus controller systemUNISYS CORP·Filed 1993·Granted May 7, 1996·10 cites·34 claims
- 1836US4947393AActivity verification system for memory or logicUNISYS CORP·Filed 1988·Granted Aug 7, 1990·7 cites·16 claims
- 1935US5649096ABus request error detectionUNISYS CORP·Filed 1995·Granted Jul 15, 1997·10 cites·5 claims
- 2034US5423030ABus station abort detectionUNISYS CORP·Filed 1993·Granted Jun 6, 1995·6 cites·3 claims
- 2133US5519876AProcessor communications bus having address lines selecting different storage locations based on selected control linesUNISYS CORP·Filed 1993·Granted May 21, 1996·5 cites·3 claims
- 2233US4953167AData bus enable verification logicUNISYS CORP·Filed 1988·Granted Aug 28, 1990·4 cites·7 claims
- 2331US5032984AData bank priority systemUNISYS CORP·Filed 1988·Granted Jul 16, 1991·4 cites·14 claims
- 2429US5257382AData bank priority systemUNISYS CORP·Filed 1991·Granted Oct 26, 1993·0 cites·8 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →