Inventor · disambiguated record
Wae Chet Yong
Also filed as: YONG WAE CHET
14 granted patents·1 pending application·24 citations·filing 2005–2021
88Inventor score
Files withINFINEON TECHNOLOGIES AG9JOB DORAISAMY STANLEY2GOLLER BERND1HENG CHAI WEI1LOW KHAI HUAT JEFFREY1
Top patents by PatentIndex Score
15 records- 0176US11133281B2Chip to chip interconnect in encapsulant of molded semiconductor packageINFINEON TECHNOLOGIES AG·Filed 2019·Granted Sep 28, 2021·2 cites·10 claims
- 0276US7732937B2Semiconductor package with mold lock ventINFINEON TECHNOLOGIES AG·Filed 2008·Granted Jun 8, 2010·7 cites·6 claims
- 0367US11569196B2Chip to chip interconnect in encapsulant of molded semiconductor packageINFINEON TECHNOLOGIES AG·Filed 2021·Granted Jan 31, 2023·0 cites·12 claims
- 0465US8110906B2Semiconductor device including isolation layerMAHLER JOACHIM·Filed 2007·Granted Feb 7, 2012·2 cites·14 claims
- 0564US7791182B2Semiconductor component having maximized bonding areas of electrically conductive members connected to semiconductor device and connected to leadframe and method of producingINFINEON TECHNOLOGIES AG·Filed 2005·Granted Sep 7, 2010·5 cites·17 claims
- 0660US8466009B2Method of fabricating a semiconductor package with mold lock openingGOLLER BERND·Filed 2010·Granted Jun 18, 2013·2 cites·14 claims
- 0759US8067841B2Semiconductor devices having a resin with warpage compensated surfacesHENG CHAI WEI·Filed 2008·Granted Nov 29, 2011·3 cites·25 claims
- 0858US7821141B2Semiconductor deviceINFINEON TECHNOLOGIES AG·Filed 2008·Granted Oct 26, 2010·1 cites·29 claims
- 0954US12094807B2Stacked transistor chip package with source couplingINFINEON TECHNOLOGIES AG·Filed 2021·Granted Sep 17, 2024·0 cites·16 claims
- 1052US8207601B2Electronic component and a method of fabricating an electronic componentLOW KHAI HUAT JEFFREY·Filed 2008·Granted Jun 26, 2012·2 cites·20 claims
- 1148US7723165B2Method of forming component packageINFINEON TECHNOLOGIES AG·Filed 2008·Granted May 25, 2010·0 cites·19 claims
- 1246US8377753B2Method of fabricating a semiconductor device having a resin with warpage compensated structuresINFINEON TECHNOLOGIES AG·Filed 2011·Granted Feb 19, 2013·0 cites·29 claims
- 1340US10978378B2Encapsulated leadless package having an at least partially exposed interior sidewall of a chip carrierINFINEON TECHNOLOGIES AG·Filed 2018·Granted Apr 13, 2021·0 cites·13 claims
- 1432US8169069B2Integrated semiconductor outline packageJOB DORAISAMY STANLEY·Filed 2006·Granted May 1, 2012·0 cites·25 claims
- 1531US2012162924A1Integrated Semiconductor Outline PackageJOB DORAISAMY STANLEY·Filed 2012·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Wae Chet Yong files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →