Inventor · disambiguated record
Wen-Hao Chen
Also filed as: CHEN WEN · CHEN WEN G · CHEN WEN HAO
107 granted patents·26 pending applications·328 citations·filing 2001–2025
99Inventor score
Files withTAIWAN SEMICONDUCTOR MFG CO LTD88TAIWAN SEMICONDUCTOR MFG10CHEN WEN-HAO5NUCRYST PHARMACEUTICALS4UNIV NAT CENTRAL4
Top patents by PatentIndex Score
133 records- 0198US11449656B2Method of designing semiconductor deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Sep 20, 2022·5 cites·20 claims
- 0298US11275886B2Integrated circuit and method of forming same and a systemTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Mar 15, 2022·8 cites·20 claims
- 0396US11727185B2System for designing semiconductor deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Aug 15, 2023·2 cites·20 claims
- 0496US11681853B2Integrated circuit and method of forming same and a systemTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Jun 20, 2023·3 cites·20 claims
- 0595US12014131B2Integrated circuit and method of forming same and a systemTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Jun 18, 2024·2 cites·20 claims
- 0695US11256844B2Cell row arrangement in regions of integrated circuit layoutTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Feb 22, 2022·4 cites·20 claims
- 0795US8601409B1Compression method and system for use with multi-patterningCHEN HUANG-YU·Filed 2012·Granted Dec 3, 2013·30 cites·21 claims
- 0894US12009356B2Integrated circuit and method of forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Jun 11, 2024·2 cites·20 claims
- 0994US11030383B2Integrated device and method of forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Jun 8, 2021·4 cites·20 claims
- 1094US10990745B2Integrated circuit and method of forming same and a systemTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Apr 27, 2021·7 cites·20 claims
- 1193US11263378B2Multi-row standard cell design method in hybrid row height systemTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Mar 1, 2022·3 cites·20 claims
- 1293US9911697B2Power strap structure for high performance and low current densityTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Mar 6, 2018·8 cites·20 claims
- 1393US9262570B2Layout boundary methodTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2013·Granted Feb 16, 2016·26 cites·18 claims
- 1492US11928416B2Semiconductor process technology assessmentTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Mar 12, 2024·2 cites·20 claims
- 1592US11604915B2Semiconductor process technology assessmentTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Mar 14, 2023·3 cites·20 claims
- 1691US11942941B2Multiple supply voltage tracks and standard cellsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Mar 26, 2024·1 cites·20 claims
- 1791US10872190B2Method and system for latch-up preventionTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Dec 22, 2020·5 cites·20 claims
- 1891US9971863B2Rule checking for multiple patterning technologyTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted May 15, 2018·7 cites·20 claims
- 1990US10678991B2Integrated device and method of forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Jun 9, 2020·7 cites·20 claims
- 2090US10289794B2Layout for semiconductor device including via pillar structureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted May 14, 2019·5 cites·20 claims
- 2190US9977857B1Method and circuit for via pillar optimizationTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted May 22, 2018·8 cites·20 claims
- 2290US9558312B2Electromigration resistant standard cell deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Jan 31, 2017·7 cites·20 claims
- 2390US8959466B1Systems and methods for designing layouts for semiconductor device fabricationTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Feb 17, 2015·6 cites·20 claims
- 2489US10089433B2Method for triple-patterning friendly placementTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Oct 2, 2018·6 cites·20 claims
- 2588US10510688B2Via rail solution for high power electromigrationTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Dec 17, 2019·4 cites·20 claims
- 2688US10170422B2Power strap structure for high performance and low current densityTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Jan 1, 2019·4 cites·20 claims
- 2788US9477803B2Method of generating techfile having reduced corner variation valueTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2014·Granted Oct 25, 2016·9 cites·20 claims
- 2887US9380709B2Method of cutting conductive patternsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2013·Granted Jun 28, 2016·5 cites·18 claims
- 2987US8431968B2Electromigration resistant standard cell deviceLU LEE-CHUNG·Filed 2010·Granted Apr 30, 2013·8 cites·20 claims
- 3086US10956650B1Systems and methods for improving design performance through placement of functional and spare cells by leveraging LDE effectTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Mar 23, 2021·2 cites·20 claims
- 3186US10275562B2Method of decomposing a layout for multiple-patterning lithographyTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Apr 30, 2019·3 cites·20 claims
- 3285US12400067B2Integrated circuit and method of forming same and a systemTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Granted Aug 26, 2025·0 cites·20 claims
- 3385US10360342B2Method, system, and storage medium for engineering change order scheme in circuit designTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Jul 23, 2019·4 cites·20 claims
- 3485US9087170B2Cell layout design and methodTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2013·Granted Jul 21, 2015·8 cites·20 claims
- 3585US9035361B2Electromigration resistant standard cell deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2013·Granted May 19, 2015·6 cites·20 claims
- 3685US8316340B2Fixing full-chip violations using flip-flopsCHEN WEN-HAO·Filed 2010·Granted Nov 20, 2012·10 cites·12 claims
- 3784US10515186B2Method of decomposing a layout for multiple-patterning lithographyTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Dec 24, 2019·2 cites·20 claims
- 3884US9563731B2Cell boundaries for self aligned multiple patterning abutmentsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2014·Granted Feb 7, 2017·4 cites·19 claims
- 3984US8977991B2Method and system for replacing a pattern in a layoutTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2013·Granted Mar 10, 2015·6 cites·20 claims
- 4083US12353819B2Semiconductor device for regulating integrated circuit timing and power consumptionTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Granted Jul 8, 2025·0 cites·20 claims
- 4183US12199609B2Multiple supply voltage tracks and standard cellsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Granted Jan 14, 2025·0 cites·20 claims
- 4283US11514224B2Systems and methods for improving design performance through placement of functional and spare cells by leveraging LDE effectTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Nov 29, 2022·1 cites·20 claims
- 4383US10817643B2Method of designing semiconductor device and system for implementing the methodTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Oct 27, 2020·2 cites·20 claims
- 4483US8914755B1Layout re-decomposition for multiple patterning layoutsTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Dec 16, 2014·7 cites·20 claims
- 4583US8601408B2Method and system for replacing a pattern in a layoutCHEN HUANG-YU·Filed 2011·Granted Dec 3, 2013·6 cites·19 claims
- 4682US9317650B2Double patterning technology (DPT) layout routingTAIWAN SEMICONDUCTOR MFG·Filed 2014·Granted Apr 19, 2016·5 cites·20 claims
- 4782US2024386180A1Method and system for latch-up preventionTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 4881US12024098B2Windshield trim panel clipsCHEN WEN·Filed 2021·Granted Jul 2, 2024·1 cites·17 claims
- 4981US12013643B2Method of cutting conductive patternsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Jun 18, 2024·0 cites·20 claims
- 5081US10861790B2Power strap structure for high performance and low current densityTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Dec 8, 2020·2 cites·20 claims
Showing the top 50 of 133 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →