Inventor · disambiguated record
Wei-Ray Lin
Also filed as: LIN WEI-RAY
16 granted patents·5 pending applications·311 citations·filing 1997–2025
94Inventor score
Top patents by PatentIndex Score
21 records- 0182US10510623B2Overlay error and process window metrologyTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Dec 17, 2019·3 cites·20 claims
- 0280US6255161B1Method of forming a capacitor and a contact plugNANYA TECHNOLOGY CORP·Filed 2000·Granted Jul 3, 2001·32 cites·22 claims
- 0379US2025357320A1Delamination detection structureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 0476US6184081B1Method of fabricating a capacitor under bit line DRAM structure using contact hole linersVANGUARD INT SEMICONDUCT CORP·Filed 1999·Granted Feb 6, 2001·57 cites·26 claims
- 0575US6329241B1Methods for producing capacitor-node contact plugs of dynamic random-access memoryNANYA TECHNOLOGY CORP·Filed 2000·Granted Dec 11, 2001·24 cites·19 claims
- 0673US6057210AMethod of making a shallow trench isolation for ULSI formation via in-direct CMP processVANGUARD INT SEMICONDUCT CORP·Filed 1998·Granted May 2, 2000·46 cites·20 claims
- 0772US2025140684A1Delamination detection structureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 0863US6261923B1Method to solve the dishing issue in CMP planarization by using a nitride hard mask for local inverse etchback and CMPVANGUARD INT SEMICONDUCT CORP·Filed 1999·Granted Jul 17, 2001·30 cites·21 claims
- 0960US2025233026A1Semiconductor device and method for fabricating the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 1060US2025239495A1Semiconductor die and wafer bonding crack detector structures and methods of forming sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 1159US6248643B1Method of fabricating a self-aligned contactVANGUARD INT SEMICONDUCT CORP·Filed 1999·Granted Jun 19, 2001·25 cites·16 claims
- 1258US10879135B2Overlay error and process window metrologyTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Dec 29, 2020·0 cites·20 claims
- 1357US6130128AMethod of fabricating crown capacitorNANYA TECHNOLOGY CORP·Filed 1999·Granted Oct 10, 2000·18 cites·22 claims
- 1456US6001704AMethod of fabricating a shallow trench isolation by using oxide/oxynitride layersVANGUARD INT SEMICONDUCT CORP·Filed 1998·Granted Dec 14, 1999·22 cites·15 claims
- 1555US2024047384A1Method of manufacturing a semiconductor device and a semiconductor deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Application pending·0 cites
- 1652US6187625B1Method of fabricating crown capacitorNANYA TECHNOLOGY CORP·Filed 1999·Granted Feb 13, 2001·17 cites·23 claims
- 1745US6180489B1Formation of finely controlled shallow trench isolation for ULSI processVANGUARD INT SEMICONDUCT CORP·Filed 1999·Granted Jan 30, 2001·12 cites·20 claims
- 1841US6159821AMethods for shallow trench isolationVANGUARD INT SEMICONDUCT CORP·Filed 1999·Granted Dec 12, 2000·10 cites·19 claims
- 1937US6117740AMethod of forming a shallow trench isolation by using PE-oxide and PE-nitride multi-layerVANGUARD INT SEMICONDUCT CORP·Filed 1998·Granted Sep 12, 2000·7 cites·12 claims
- 2036US6060348AMethod to fabricate isolation by combining locos and shallow trench isolation for ULSI technologyVANGUARD INT SEMICONDUCT CORP·Filed 1998·Granted May 9, 2000·6 cites·20 claims
- 2132US6143664AMethod of planarizing a structure having an interpoly layerVANGUARD INT SEMICONDUCT CORP·Filed 1997·Granted Nov 7, 2000·2 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →