Inventor · disambiguated record
William K. Barth
Also filed as: BARTH WILLIAM · BARTH WILLIAM K
7 granted patents·2 pending applications·250 citations·filing 2002–2005
87Inventor score
Top patents by PatentIndex Score
9 records- 0193US6969651B1Layout design and process to form nanotube cell for nanotube memory applicationsLSI LOGIC CORP·Filed 2004·Granted Nov 29, 2005·140 cites·17 claims
- 0286US7160805B1Inter-layer interconnection structure for large electrical connectionsLSI LOGIC CORP·Filed 2003·Granted Jan 9, 2007·41 cites·13 claims
- 0377US6998343B1Method for creating barrier layers for copper diffusionLSI LOGIC CORP·Filed 2003·Granted Feb 14, 2006·26 cites·17 claims
- 0475US6642597B1Inter-layer interconnection structure for large electrical connectionsLSI LOGIC CORP·Filed 2002·Granted Nov 4, 2003·20 cites·17 claims
- 0568US7033929B1Dual damascene interconnect structure with improved electro migration lifetimesLSI LOGIC CORP·Filed 2002·Granted Apr 25, 2006·13 cites·25 claims
- 0658US7312532B2Dual damascene interconnect structure with improved electro migration lifetimesLSI CORP·Filed 2005·Granted Dec 25, 2007·1 cites·7 claims
- 0758US6838379B1Process for reducing impurity levels, stress, and resistivity, and increasing grain size of copper filler in trenches and vias of integrated circuit structures to enhance electrical performance of copper fillerLSI LOGIC CORP·Filed 2003·Granted Jan 4, 2005·9 cites·16 claims
- 0839US2005224358A1Method for improved local planarity control during electropolishingLSI LOGIC CORP·Filed 2004·Application pending·0 cites
- 0935US2004207093A1Method of fabricating an alloy cap layer over CU wires to improve electromigration performance of CU interconnectsFiled 2003·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →