Inventor · disambiguated record
William M. Buros
Also filed as: BUROS WILLIAM M
1 granted patent·2 pending applications·1 citations·filing 2006–2009
16Inventor score
Technology areasG06F
Top patents by PatentIndex Score
3 records- 0143US9032411B2Logical extended map to demonstrate core activity including L2 and L3 cache hit and miss ratioARNDT BARRY B·Filed 2009·Granted May 12, 2015·1 cites·6 claims
- 0237US2008196030A1Optimizing memory accesses for multi-threaded programs in a non-uniform memory access (numa) systemBUROS WILLIAM M·Filed 2007·Application pending·0 cites
- 0336US2008104362A1Method and System for Performance-Driven Memory Page Size PromotionBUROS WILLIAM M·Filed 2006·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →