Inventor · disambiguated record
William Kurt Lewchuk
Also filed as: LEWCHUK WILLIAM K · LEWCHUK WILLIAM KURT
11 granted patents·221 citations·filing 1994–2009
91Inventor score
Technology areasG06F
Top patents by PatentIndex Score
11 records- 0173US6473832B1Load/store unit having pre-cache and post-cache queues for low latency load memory operationsADVANCED MICRO DEVICES INC·Filed 1999·Granted Oct 29, 2002·66 cites·23 claims
- 0263US8589629B2Method for way allocation and way locking in a cacheOWEN JONATHAN·Filed 2009·Granted Nov 19, 2013·3 cites·21 claims
- 0356US6446189B1Computer system including a novel address translation mechanismADVANCED MICRO DEVICES INC·Filed 1999·Granted Sep 3, 2002·31 cites·24 claims
- 0456US5659708ACache coherency in a multiprocessing systemIBM·Filed 1994·Granted Aug 19, 1997·28 cites·26 claims
- 0549US5771247ALow latency error reporting for high performance busIBM·Filed 1996·Granted Jun 23, 1998·21 cites·12 claims
- 0649US5608878ADual latency status and coherency reporting for a multiprocessing systemIBM·Filed 1994·Granted Mar 4, 1997·19 cites·20 claims
- 0744US6415360B1Minimizing self-modifying code checks for uncacheable memory typesADVANCED MICRO DEVICES INC·Filed 1999·Granted Jul 2, 2002·15 cites·35 claims
- 0843US6430639B1Minimizing use of bus command code points to request the start and end of a lockADVANCED MICRO DEVICES INC·Filed 1999·Granted Aug 6, 2002·15 cites·36 claims
- 0937US5745698ASystem and method for communicating between devicesIBM·Filed 1996·Granted Apr 28, 1998·9 cites·42 claims
- 1037US5671370AAlternating data valid control signals for high performance data transferIBM·Filed 1996·Granted Sep 23, 1997·9 cites·17 claims
- 1133US5687327ASystem and method for allocating bus resources in a data processing systemIBM·Filed 1994·Granted Nov 11, 1997·5 cites·14 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →