Inventor · disambiguated record
William C. Van Loo
Also filed as: VAN LOO WILLIAM · VAN LOO WILLIAM C
32 granted patents·1 pending application·2,224 citations·filing 1979–2002
98Inventor score
Top patents by PatentIndex Score
33 records- 0196US5655100ATransaction activation processor for controlling memory transaction execution in a packet switched cache coherent multiprocessor systemSUN MICROSYSTEMS INC·Filed 1995·Granted Aug 5, 1997·288 cites·10 claims
- 0295US6233615B1System for maintaining strongly sequentially ordered packet flow in a ring network system with busy and failed nodesSUN MICROSYSTEMS INC·Filed 2000·Granted May 15, 2001·102 cites·5 claims
- 0392US5905998ATransaction activation processor for controlling memory transaction processing in a packet switched cache coherent multiprocessor systemSUN MICROSYSTEMS INC·Filed 1997·Granted May 18, 1999·176 cites·8 claims
- 0492US4271468AMultiprocessor mechanism for handling channel interruptsIBM·Filed 1979·Granted Jun 2, 1981·121 cites·26 claims
- 0589US5644753AFast, dual ported cache controller for data processors in a packet switched cache coherent multiprocessor systemSUN MICROSYSTEMS INC·Filed 1996·Granted Jul 1, 1997·164 cites·7 claims
- 0687US5634068APacket switched cache coherent multiprocessor systemSUN MICROSYSTEMS INC·Filed 1995·Granted May 27, 1997·147 cites·11 claims
- 0785US5692197AMethod and apparatus for reducing power consumption in a computer network without sacrificing performanceSUN MICROSYSTEMS INC·Filed 1995·Granted Nov 25, 1997·126 cites·17 claims
- 0883US6463472B1System for maintaining strongly sequentially ordered packet flow in a ring network system with busy and failed nodesSUN MICROSYSTEMS INC·Filed 2001·Granted Oct 8, 2002·30 cites·12 claims
- 0983US5581729AParallelized coherent read and writeback transaction processing system for use in a packet switched cache coherent multiprocessor systemSUN MICROSYSTEMS INC·Filed 1995·Granted Dec 3, 1996·121 cites·16 claims
- 1081US5684977AWriteback cancellation processing system for use in a packet switched cache coherent multiprocessor systemSUN MICROSYSTEMS INC·Filed 1995·Granted Nov 4, 1997·104 cites·4 claims
- 1181US5263142AInput/output cache with mapped pages allocated for caching direct (virtual) memory access input/output data based on type of I/O devicesSUN MICROSYSTEMS INC·Filed 1992·Granted Nov 16, 1993·93 cites·5 claims
- 1280US5892957AMethod and apparatus for interrupt communication in packet-switched microprocessor-based computer systemSUN MICROSYSTEMS INC·Filed 1997·Granted Apr 6, 1999·81 cites·20 claims
- 1379US6381664B1System for multisized bus coupling in a packet-switched computer systemSUN MICROSYSTEMS INC·Filed 2000·Granted Apr 30, 2002·22 cites·21 claims
- 1479US5657472AMemory transaction execution system and method for multiprocessor system having independent parallel transaction queues associated with each processorSUN MICROSYSTEMS INC·Filed 1995·Granted Aug 12, 1997·95 cites·13 claims
- 1578US5247648AMaintaining data coherency between a central cache, an I/O cache and a memorySUN MICROSYSTEMS INC·Filed 1992·Granted Sep 21, 1993·82 cites·16 claims
- 1675US6597665B1System for dynamic ordering support in a ringlet serial interconnectSUN MICROSYSTEMS INC·Filed 2000·Granted Jul 22, 2003·18 cites·11 claims
- 1773US5689713AMethod and apparatus for interrupt communication in a packet-switched computer systemSUN MICROSYSTEMS INC·Filed 1995·Granted Nov 18, 1997·59 cites·20 claims
- 1872US6101565ASystem for multisized bus coupling in a packet-switched computer systemSUN MICROSYSTEMS INC·Filed 1997·Granted Aug 8, 2000·50 cites·21 claims
- 1967US6662306B2Fast forwarding slave requests in a packet-switched computer system by transmitting request to slave in advance to avoid arbitration delay when system controller validates requestSUN MICROSYSTEMS INC·Filed 2001·Granted Dec 9, 2003·9 cites·4 claims
- 2067US5854906AMethod and apparatus for fast-forwarding slave request in a packet-switched computer systemSUN MICROSYSTEMS INC·Filed 1997·Granted Dec 29, 1998·39 cites·4 claims
- 2163US6065052ASystem for maintaining strongly sequentially ordered packet flow in a ring network system with busy and failed nodesSUN MICROSYSTEMS INC·Filed 1996·Granted May 16, 2000·39 cites·28 claims
- 2261US5710891APipelined distributed bus arbitration systemSUN MICROSYSTEMS INC·Filed 1995·Granted Jan 20, 1998·35 cites·5 claims
- 2360US5919265ASource synchronization data transfers without resynchronization penaltySUN MICROSYSTEMS INC·Filed 1996·Granted Jul 6, 1999·42 cites·6 claims
- 2459US5907485AMethod and apparatus for flow control in packet-switched computer systemSUN MICROSYSTEMS INC·Filed 1995·Granted May 25, 1999·36 cites·21 claims
- 2554US5852718AMethod and apparatus for hybrid packet-switched and circuit-switched flow control in a computer systemSUN MICROSYSTEMS INC·Filed 1995·Granted Dec 22, 1998·29 cites·23 claims
- 2652US5161162AMethod and apparatus for system bus testability through loopbackSUN MICROSYSTEMS INC·Filed 1990·Granted Nov 3, 1992·29 cites·17 claims
- 2750US5864677ASystem for preserving sequential ordering and supporting nonidempotent commands in a ring network with busy nodesSUN MICROSYSTEMS INC·Filed 1996·Granted Jan 26, 1999·26 cites·31 claims
- 2849US6260174B1Method and apparatus for fast-forwarding slave requests in a packet-switched computer systemSUN MICROSYSTEMS INC·Filed 1998·Granted Jul 10, 2001·16 cites·8 claims
- 2945US6064672ASystem for dynamic ordering support in a ringlet serial interconnectSUN MICROSYSTEMS INC·Filed 1996·Granted May 16, 2000·16 cites·22 claims
- 3045US2002194418A1System for multisized bus coupling in a packet-switched computer systemSUN MICROSYSTEMS INC·Filed 2002·Application pending·0 cites
- 3144US5862356APipelined distributed bus arbitration systemSUN MICROSYSTEMS INC·Filed 1997·Granted Jan 19, 1999·14 cites·10 claims
- 3242US5987579AMethod and apparatus for quickly initiating memory accesses in a multiprocessor cache coherent computer systemSUN MICROSYSTEMS INC·Filed 1997·Granted Nov 16, 1999·14 cites·21 claims
- 3330US5737755ASystem level mechanism for invalidating data stored in the external cache of a processor in a computer systemSUN MICROSYSTEMS INC·Filed 1997·Granted Apr 7, 1998·1 cites·9 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →