Inventor · disambiguated record
William G. Walker
Also filed as: WALKER WILLIAM G · WALKER WILLIAM GORDON
24 granted patents·374 citations·filing 1973–2016
97Inventor score
Files withVIRTUAL SILICON TECHNOLOGY INC4MOSAID TECHNOLOGIES INC3TRINITY IND INC3VLSI TECHNOLOGY INC3CONVERSANT INTELLECTUAL PROPERTY MAN INC2
Top patents by PatentIndex Score
24 records- 0195US7348804B2Low leakage and data retention circuitryMOSAID DELAWARE INC·Filed 2007·Granted Mar 25, 2008·25 cites·33 claims
- 0295US7227383B2Low leakage and data retention circuitryMOSAID DELAWARE INC·Filed 2005·Granted Jun 5, 2007·27 cites·16 claims
- 0393US8253438B2Low leakage and data retention circuitryHOBERMAN BARRY A·Filed 2011·Granted Aug 28, 2012·11 cites·19 claims
- 0492US5427227ABaggage conveyor systemTRINITY IND INC·Filed 1994·Granted Jun 27, 1995·63 cites·12 claims
- 0587US8854077B2Low leakage and data retention circuitryHOBERMAN BARRY A·Filed 2012·Granted Oct 7, 2014·5 cites·18 claims
- 0687US5231311ADigital output buffer and method with slew rate control and reduced crowbar currentVLSI TECHNOLOGY INC·Filed 1991·Granted Jul 27, 1993·55 cites·4 claims
- 0782US7592837B2Low leakage and data retention circuitryMOSAID TECHNOLOGIES CORP·Filed 2008·Granted Sep 22, 2009·10 cites·63 claims
- 0881US5111075AReduced switching noise output buffer using diode for quick turn-offVLSI TECHNOLOGY INC·Filed 1991·Granted May 5, 1992·37 cites·19 claims
- 0980US7940081B2Low leakage and data retention circuitryMOSAID TECHNOLOGIES INC·Filed 2009·Granted May 10, 2011·5 cites·20 claims
- 1080US7508256B2Integrated circuit with signal bus formed by cell abutment of logic cellsMOSAID TECHNOLOGIES CORP·Filed 2006·Granted Mar 24, 2009·8 cites·23 claims
- 1179US7443197B2Low leakage and data retention circuitryMOSAID TECHNOLOGIES INC·Filed 2007·Granted Oct 28, 2008·6 cites·47 claims
- 1277US4123382AMethod of microencapsulationMERCK & CO INC·Filed 1973·Granted Oct 31, 1978·28 cites·6 claims
- 1370US9350349B2Low leakage and data retention circuitryCONVERSANT INTELLECTUAL PROPERTY MAN INC·Filed 2014·Granted May 24, 2016·1 cites·16 claims
- 1467US6839882B2Method and apparatus for design of integrated circuitsVIRTUAL SILICON TECHNOLOGY INC·Filed 2002·Granted Jan 4, 2005·11 cites·30 claims
- 1565US8026738B2Integrated circuit with signal bus formed by cell abutment of logic cellsMOSAID TECHNOLOGIES INC·Filed 2009·Granted Sep 27, 2011·2 cites·44 claims
- 1665US7051308B2Method and apparatus for integrated circuit design with library cellsVIRTUAL SILICON TECHNOLOGY INC·Filed 2002·Granted May 23, 2006·9 cites·15 claims
- 1763US6766496B2Method and apparatus for integrated circuit design with a software toolVIRTUAL SILICON TECHNOLOGY INC·Filed 2002·Granted Jul 20, 2004·8 cites·17 claims
- 1861US4875954AMethod and apparatus for manufacturing carpetEBONWOOD LTD·Filed 1988·Granted Oct 24, 1989·22 cites·6 claims
- 1954US5263571ABaggage conveyor systemTRINITY IND INC·Filed 1993·Granted Nov 23, 1993·16 cites·13 claims
- 2054US5146306ASemiconductor FET structures with slew-rate controlVLSI TECHNOLOGY INC·Filed 1991·Granted Sep 8, 1992·13 cites·20 claims
- 2153US9722605B2Low leakage and data retention circuitryCONVERSANT INTELLECTUAL PROPERTY MAN INC·Filed 2016·Granted Aug 1, 2017·0 cites·12 claims
- 2247US5311981ABaggage conveyor systemTRINITY IND INC·Filed 1993·Granted May 17, 1994·10 cites·5 claims
- 2345US6687880B2Integrated circuit having a reduced spacing between a bus and adjacent circuitryVIRTUAL SILICON TECHNOLOGY INC·Filed 2002·Granted Feb 3, 2004·2 cites·33 claims
- 2440USRE40855EIntegrated circuit having a reduced spacing between a bus and adjacent circuitryRIVERA BILLIE JEAN·Filed 2006·Granted Jul 14, 2009·0 cites·66 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →