Inventor · disambiguated record
William E. Woods
Also filed as: LEMAY RICHARD A · WOODS WILLIAM E
42 granted patents·939 citations·filing 1975–1995
98Inventor score
Top patents by PatentIndex Score
42 records- 0192US3993981AApparatus for processing data transfer requests in a data processing systemHONEYWELL INF SYSTEMS·Filed 1975·Granted Nov 23, 1976·102 cites·16 claims
- 0284US4206503AMultiple length address formation in a microprogrammed data processing systemHONEYWELL INF SYSTEMS·Filed 1978·Granted Jun 3, 1980·51 cites·4 claims
- 0384US4074353ATrap mechanism for a data processing systemHONEYWELL INF SYSTEMS·Filed 1976·Granted Feb 14, 1978·58 cites·13 claims
- 0478US4320455AQueue structure for a data processing systemHONEYWELL INF SYSTEMS·Filed 1979·Granted Mar 16, 1982·39 cites·10 claims
- 0578US4099255AInterrupt apparatus for enabling interrupt service in response to time out conditionsHONEYWELL INF SYSTEMS·Filed 1976·Granted Jul 4, 1978·37 cites·8 claims
- 0678US4079451AWord, byte and bit indexed addressing in a data processing systemHONEYWELL INF SYSTEMS·Filed 1976·Granted Mar 14, 1978·38 cites·12 claims
- 0778US3984820AApparatus for changing the interrupt level of a process executing in a data processing systemHONEYWELL INF SYSTEMS·Filed 1975·Granted Oct 5, 1976·37 cites·10 claims
- 0877US5442866ASurveying rule assembly, and methods of constructing and utilizing sameFiled 1992·Granted Aug 22, 1995·38 cites·10 claims
- 0974US4020471AInterrupt scan and processing system for a data processing systemHONEYWELL INF SYSTEMS·Filed 1975·Granted Apr 26, 1977·34 cites·16 claims
- 1068US4363095AHit/miss logic for a cache memoryHONEYWELL INF SYSTEMS·Filed 1980·Granted Dec 7, 1982·35 cites·13 claims
- 1167US5678032AMethod of optimizing the execution of program instuctions by an emulator using a plurality of execution unitsBULL HN INFORMATION SYST·Filed 1995·Granted Oct 14, 1997·60 cites·21 claims
- 1265US4799181ABCD arithmetic using binary arithmetic and logical operationsHONEYWELL BULL·Filed 1986·Granted Jan 17, 1989·34 cites·36 claims
- 1362US5983012AExecuting programs of a first system on a second systemBULL HN INFORMATION SYST·Filed 1993·Granted Nov 9, 1999·45 cites·9 claims
- 1461US4047247AAddress formation in a microprogrammed data processing systemHONEYWELL INF SYSTEMS·Filed 1976·Granted Sep 6, 1977·22 cites·3 claims
- 1557US5136500AMultiple shared memory arrangement wherein multiple processors individually and concurrently access any one of plural memoriesHONEYWELL INF SYSTEMS·Filed 1989·Granted Aug 4, 1992·24 cites·11 claims
- 1655US5375248AMethod for organizing state machine by selectively grouping status signals as inputs and classifying commands to be executed into performance sensitive and nonsensitive categoriesBULL HN INFORMATION SYST·Filed 1993·Granted Dec 20, 1994·24 cites·2 claims
- 1751US4432050AData processing system write protection mechanismHARRIS ROBERT J·Filed 1980·Granted Feb 14, 1984·22 cites·6 claims
- 1850US4225921ATransfer control technique between two units included in a data processing systemHONEYWELL INF SYSTEMS·Filed 1978·Granted Sep 30, 1980·14 cites·15 claims
- 1949US5515525AEmulating the memory functions of a first system on a second systemBULL HN INFORMATION SYST·Filed 1993·Granted May 7, 1996·28 cites·4 claims
- 2048US4491908AMicroprogrammed control of extended integer and commercial instruction processor instructions through use of a data type field in a central processor unitHONEYWELL INF SYSTEMS·Filed 1981·Granted Jan 1, 1985·15 cites·5 claims
- 2148US4245299ASystem providing adaptive response in information requesting unitHONEYWELL INF SYSTEMS·Filed 1978·Granted Jan 13, 1981·12 cites·13 claims
- 2247US4604685ATwo stage selection based on time of arrival and predetermined priority in a bus priority resolverHONEYWELL INF SYSTEMS·Filed 1984·Granted Aug 5, 1986·15 cites·12 claims
- 2347US4455606ALogic control system for efficient memory to CPU transfersHONEYWELL INF SYSTEMS·Filed 1981·Granted Jun 19, 1984·14 cites·4 claims
- 2446US5280595AState machine for executing commands within a minimum number of cycles by accomodating unforseen time dependency according to status signals received from different functional sectionsBULL HN INFORMATION SYST·Filed 1990·Granted Jan 18, 1994·15 cites·13 claims
- 2544US4451883ABus sourcing and shifter control of a central processing unitHONEYWELL INF SYSTEMS·Filed 1981·Granted May 29, 1984·13 cites·12 claims
- 2643US4837738AAddress boundary detectorHONEYWELL INF SYSTEMS·Filed 1986·Granted Jun 6, 1989·12 cites·2 claims
- 2742US4964037AMemory addressing arrangementBULL HN INFORMATION SYST·Filed 1987·Granted Oct 16, 1990·11 cites·1 claims
- 2842US4811266AMultifunction arithmetic indicatorHONEYWELL BULL·Filed 1986·Granted Mar 7, 1989·11 cites·3 claims
- 2942US4308589AApparatus for performing the scientific add instructionHONEYWELL INF SYSTEMS·Filed 1979·Granted Dec 29, 1981·9 cites·14 claims
- 3042US4236210AArchitecture for a control store included in a data processing systemHONEYWELL INF SYSTEMS·Filed 1978·Granted Nov 25, 1980·11 cites·24 claims
- 3139US4460959ALogic control system including cache memory for CPU-memory transfersHONEYWELL INF SYSTEMS·Filed 1981·Granted Jul 17, 1984·9 cites·3 claims
- 3237US4935737AData selection matrixBULL HN INFORMATION SYST·Filed 1986·Granted Jun 19, 1990·8 cites·4 claims
- 3336US4472773AInstruction decoding logic systemHONEYWELL INF SYSTEMS·Filed 1981·Granted Sep 18, 1984·7 cites·4 claims
- 3435US4727486AHardware demand fetch cycle system interfaceHONEYWELL INF SYSTEMS·Filed 1986·Granted Feb 23, 1988·7 cites·12 claims
- 3535US4305134AAutomatic operand length control of the result of a scientific arithmetic operationHONEYWELL INF SYSTEMS·Filed 1979·Granted Dec 8, 1981·5 cites·6 claims
- 3633US5161217ABuffered address stack register with parallel input registers and overflow protectionBULL HN INFORMATION SYST·Filed 1989·Granted Nov 3, 1992·5 cites·4 claims
- 3733US4349874ABuffer system for supply procedure words to a central processor unitHONEYWELL INF SYSTEMS·Filed 1980·Granted Sep 14, 1982·5 cites·11 claims
- 3832US5243601AApparatus and method for detecting a runaway firmware control unitBULL HN INFORMATION SYST·Filed 1990·Granted Sep 7, 1993·4 cites·24 claims
- 3931US4467416ALogic transfer and decoding systemHONEYWELL INF SYSTEMS·Filed 1981·Granted Aug 21, 1984·3 cites·4 claims
- 4031US4348723AControl store test selection logic for a data processing systemHONEYWELL INF SYSTEMS·Filed 1980·Granted Sep 7, 1982·3 cites·6 claims
- 4130US4467417AFlexible logic transfer and instruction decoding systemHONEYWELL INF SYSTEMS·Filed 1981·Granted Aug 21, 1984·2 cites·3 claims
- 4225US4775929ATime partitioned bus arrangementHONEYWELL BULL·Filed 1986·Granted Oct 4, 1988·1 cites·7 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →