Inventor · disambiguated record
Woo Tag Kang
Also filed as: KANG WOO TAG
16 granted patents·13 pending applications·470 citations·filing 1997–2024
94Inventor score
Top patents by PatentIndex Score
29 records- 0193US6537885B1Transistor and method of manufacturing a transistor having a shallow junction formation using a two step EPI layerINFINEON TECHNOLOGIES AG·Filed 2002·Granted Mar 25, 2003·90 cites·16 claims
- 0292US6130457ASemiconductor-on-insulator devices having insulating layers therein with self-aligned openingsSAMSUNG ELECTRONICS CO LTD·Filed 1998·Granted Oct 10, 2000·127 cites·5 claims
- 0387US6326270B1Methods of forming integrated circuit memory devices using masking layers to inhibit overetching of impurity regions and conductive linesSAMSUNG ELECTRONICS CO LTD·Filed 1999·Granted Dec 4, 2001·101 cites·17 claims
- 0482US5877046AMethods of forming semiconductor-on-insulator substratesSAMSUNG ELECTRONICS CO LTD·Filed 1997·Granted Mar 2, 1999·59 cites·18 claims
- 0575US6417547B2Semiconductor device with a halo structureSAMSUNG ELECTRONICS CO LTD·Filed 2001·Granted Jul 9, 2002·18 cites·6 claims
- 0671US6258645B1Halo structure for CMOS transistors and method of manufacturing the sameSAMSUNG ELECTRONICS CO LTD·Filed 2000·Granted Jul 10, 2001·15 cites·11 claims
- 0770US6930357B2Active SOI structure with a body contact through an insulatorINFINEON TECHNOLOGIES AG·Filed 2003·Granted Aug 16, 2005·18 cites·13 claims
- 0869US6724054B1Self-aligned contact formation using double SiN spacersINFINEON TECHNOLOGIES AG·Filed 2002·Granted Apr 20, 2004·16 cites·14 claims
- 0966US12513915B2Dynamic random-access memory (DRAM) on hot compute logic for last-level-cacheQUALCOMM INC·Filed 2023·Granted Dec 30, 2025·0 cites·20 claims
- 1063US2025380406A1Vertical bank redundancy in three-dimensional stacked dynamic random-access memory (dram) for improved yieldQUALCOMM INC·Filed 2024·Application pending·0 cites
- 1163US2025380431A1High-bandwidth three-dimensional stacked memory with a base die enabling compute logic without memory power grid restrictionsQUALCOMM INC·Filed 2024·Application pending·0 cites
- 1262US9116876B2Programmable built-in-self tester (BIST) in memory controllerQUALCOMM INC·Filed 2012·Granted Aug 25, 2015·1 cites·28 claims
- 1362US8889522B2High breakdown voltage embedded MIM capacitor structureQUALCOMM INC·Filed 2013·Granted Nov 18, 2014·1 cites·14 claims
- 1462US2025391739A1Dual-liner through-silicon via (tsv) for power and signal transmissionQUALCOMM INC·Filed 2024·Application pending·0 cites
- 1562US2025336891A1Single hybrid system-on-chip (soc) die structure with high memory bandwidth and densityQUALCOMM INC·Filed 2024·Application pending·0 cites
- 1661US7439591B2Gate layer diode method and apparatusINFINEON TECHNOLOGIES AG·Filed 2004·Granted Oct 21, 2008·10 cites·26 claims
- 1761US2025385222A1High-bandwidth integrated circuit packaging of memory and logicQUALCOMM INC·Filed 2024·Application pending·0 cites
- 1861US2025380430A1High-bandwidth 3d stacked memory with a base die enabling compute logic without memory power grid restrictionsQUALCOMM INC·Filed 2024·Application pending·0 cites
- 1961US2025379188A1High-bandwidth memory (hbm) package-on-package (pop) dynamic random-access memory (dram) with semiconductor pillarsQUALCOMM INC·Filed 2024·Application pending·0 cites
- 2061US2025385209A1Bumpless fan-out wafer-level integrated circuit package including memory and logicQUALCOMM INC·Filed 2024·Application pending·0 cites
- 2161US2025386517A1High bandwidth small form factor 3d integrated circuit package including memory and logicQUALCOMM INC·Filed 2024·Application pending·0 cites
- 2260US7256441B2Partially recessed DRAM cell structureINFINEON TECHNOLOGIES AG·Filed 2005·Granted Aug 14, 2007·2 cites·22 claims
- 2360US2025336757A1Concurrent general-purpose memory die and near-memory compute die in system-in-package (sip)QUALCOMM INC·Filed 2024·Application pending·0 cites
- 2457US2025087640A1Low energy and small form factor packageQUALCOMM INC·Filed 2023·Application pending·0 cites
- 2556US2025015047A1Single-step via-last process for multi-stack wafersQUALCOMM INC·Filed 2023·Application pending·0 cites
- 2651US2016064391A1Dynamic random access memory cell including a ferroelectric capacitorQUALCOMM INC·Filed 2014·Application pending·0 cites
- 2744US9245881B2Selective fabrication of high-capacitance insulator for a metal-oxide-metal capacitorKANG WOO TAG·Filed 2009·Granted Jan 26, 2016·0 cites·45 claims
- 2838US6218273B1Methods of forming isolation trenches in integrated circuits using protruding insulating layersSAMSUNG ELECTRONICS CO LTD·Filed 1999·Granted Apr 17, 2001·8 cites·21 claims
- 2937US6080622AMethod for fabricating a DRAM cell capacitor including forming a conductive storage node by depositing and etching an insulative layer, filling with conductive material, and removing the insulative layerSAMSUNG ELECTRONICS CO LTD·Filed 1999·Granted Jun 27, 2000·4 cites·11 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →