Inventor · disambiguated record
Wolfgang Penth
Also filed as: PENTH WOLFGANG
13 granted patents·3 pending applications·44 citations·filing 2007–2024
88Inventor score
Top patents by PatentIndex Score
16 records- 0193US9406375B1Write address synchronization in 2 read/1write SRAM arraysIBM·Filed 2015·Granted Aug 2, 2016·16 cites·12 claims
- 0284US8493812B2Boost circuit for generating an adjustable boost voltageDENGLER OSAMA·Filed 2010·Granted Jul 23, 2013·13 cites·12 claims
- 0368US8422313B2Reduced power consumption memory circuitryBUETTNER STEFAN·Filed 2011·Granted Apr 16, 2013·4 cites·20 claims
- 0466US9437285B1Write address synchronization in 2 read/1write SRAM arraysIBM·Filed 2016·Granted Sep 6, 2016·2 cites·8 claims
- 0566US7495949B2Asymmetrical random access memory cell, memory comprising asymmetrical memory cells and method to operate such a memoryIBM·Filed 2007·Granted Feb 24, 2009·7 cites·11 claims
- 0657US9704567B1Stressing and testing semiconductor memory cellsIBM·Filed 2016·Granted Jul 11, 2017·1 cites·17 claims
- 0757US2025335198A1Low power late-selected caches using a set-prediction historyIBM·Filed 2024·Application pending·0 cites
- 0852US11043938B2Digital logic circuit for deterring race violations at an array test control boundary using an inverted array clock signal featureIBM·Filed 2019·Granted Jun 22, 2021·0 cites·19 claims
- 0950US9715944B1Automatic built-in self test for memory arraysIBM·Filed 2016·Granted Jul 25, 2017·1 cites·4 claims
- 1047US10367481B2Digital logic circuit for deterring race violations at an array test control boundary using an inverted array clock signal featureIBM·Filed 2018·Granted Jul 30, 2019·0 cites·1 claims
- 1146US10587248B2Digital logic circuit for deterring race violations at an array test control boundary using an inverted array clock signal featureIBM·Filed 2017·Granted Mar 10, 2020·0 cites·19 claims
- 1245US9837142B1Automated stressing and testing of semiconductor memory cellsIBM·Filed 2016·Granted Dec 5, 2017·0 cites·9 claims
- 1345US9805823B1Automated stressing and testing of semiconductor memory cellsIBM·Filed 2017·Granted Oct 31, 2017·0 cites·8 claims
- 1445US2025118360A1Memory device, assist cell and double assist cell for a memory deviceIBM·Filed 2024·Application pending·0 cites
- 1541US2025118362A1Banked sense amplifier circuit for a memory core and a memory core complexIBM·Filed 2024·Application pending·0 cites
- 1638US10984843B2RAM memory with pre-charging circuitry coupled to global bit-lines and method for reducing power consumptionIBM·Filed 2019·Granted Apr 20, 2021·0 cites·9 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →