Inventor · disambiguated record
Wu-Shiung Feng
Also filed as: FENG WU S · FENG WU-SHIUNG
18 granted patents·5 pending applications·127 citations·filing 1994–2012
93Inventor score
Top patents by PatentIndex Score
23 records- 0178USD361159SLipstick caseFENG WU S·Filed 1994·Granted Aug 8, 1995·22 cites·1 claims
- 0277US7191418B2Method and apparatus for rapidly selecting types of buffers which are inserted into the clock tree for high-speed very-large-scale-integrationUNIV CHANG GUNG·Filed 2004·Granted Mar 13, 2007·25 cites·3 claims
- 0373US7216322B2Clock tree synthesis for low power consumption and low clock skewUNIV CHANG GUNG·Filed 2004·Granted May 8, 2007·20 cites·3 claims
- 0468US7181664B2Method on scan chain reordering for lowering VLSI power consumptionUNIV CHANG GUNG·Filed 2004·Granted Feb 20, 2007·14 cites·6 claims
- 0566US7562324B2Method of designing a synchronous circuit of VLSI for clock skew scheduling and optimizationUNIV CHANG GUNG·Filed 2006·Granted Jul 14, 2009·4 cites·3 claims
- 0664US7600206B2Method of estimating the signal delay in a VLSI circuitUNIV CHANG GUNG·Filed 2007·Granted Oct 6, 2009·4 cites·4 claims
- 0760US7254790B2Method of moment computations in R(L)C interconnects of high speed VLSI with resistor loopsUNIV CHANG GUNG·Filed 2004·Granted Aug 7, 2007·8 cites·3 claims
- 0859US7398499B2Method of searching paths suffering from the electrostatic discharge in the process of an integrated circuit designUNIV CHANG GUNG·Filed 2006·Granted Jul 8, 2008·2 cites·6 claims
- 0958US7216309B2Method and apparatus for model-order reduction and sensitivity analysisUNIV CHANG GUNG·Filed 2004·Granted May 8, 2007·6 cites·9 claims
- 1058US7017130B2Method of verification of estimating crosstalk noise in coupled RLC interconnects with distributed line in nanometer integrated circuitsUNIV CHANG GUNG·Filed 2004·Granted Mar 21, 2006·7 cites·2 claims
- 1157US7124381B2Method of estimating crosstalk noise in lumped RLC coupled interconnectsUNIV CHANG GUNG·Filed 2004·Granted Oct 17, 2006·7 cites·4 claims
- 1254US7738947B2Biomedical signal instrumentation amplifierUNIV CHANG GUNG·Filed 2006·Granted Jun 15, 2010·3 cites·1 claims
- 1350US7797140B2Generalizations of adjoint networks techniques for RLC interconnects model-order reductionsUNIV CHANG GUNG·Filed 2004·Granted Sep 14, 2010·2 cites·2 claims
- 1445US7373367B2Efficient digital filter design tool for approximating an FIR filter with a low-order linear-phase IIR filterUNIV CHANG GUNG·Filed 2004·Granted May 13, 2008·3 cites·1 claims
- 1545US2006100830A1Moment computations of nonuniform distributed coupled RLC trees with applications to estimating crosstalk noiseUNIV CHANG GUNG·Filed 2004·Application pending·0 cites
- 1643US7512525B2Multi-point model reductions of VLSI interconnects using the rational Arnoldi method with adaptive ordersUNIV CHANG GUNG·Filed 2005·Granted Mar 31, 2009·0 cites·8 claims
- 1743US2008126028A1Method of reducing a multiple-inputs multiple-outputs (MIMO) interconnect circuit system in a global lanczos algorithmUNIV CHANG GUNG·Filed 2006·Application pending·0 cites
- 1842US7437689B2Interconnect model-order reduction methodUNIV CHANG GUNG·Filed 2005·Granted Oct 14, 2008·0 cites·4 claims
- 1942US2007255538A1Method of developing an analogical VLSI macro model in a global Arnoldi algorithmUNIV CHANG GUNG·Filed 2006·Application pending·0 cites
- 2041US7509243B2Method of determining high-speed VLSI reduced-order interconnect by non-symmetric lanczos algorithmUNIV CHANG GUNG·Filed 2005·Granted Mar 24, 2009·0 cites·2 claims
- 2140US9181167B2Chemically-modified graphene and method for producing the sameHUA MU-YI·Filed 2012·Granted Nov 10, 2015·0 cites·3 claims
- 2238US2008318372A1Manufacturing method of high-linearity and high-power cmos structureCHIU HSIEN-CHIN·Filed 2008·Application pending·0 cites
- 2336US2008157210A1High-linearity and high-power CMOS structure and manufacturing method for the sameUNIV CHANG GUNG·Filed 2006·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →