Inventor · disambiguated record
Wuping Liu
Also filed as: LIU WUPING
16 granted patents·4 pending applications·52 citations·filing 2002–2014
90Inventor score
Top patents by PatentIndex Score
20 records- 0192US8358007B2Integrated circuit system employing low-k dielectrics and method of manufacture thereofGLOBALFOUNDRIES SG PTE LTD·Filed 2010·Granted Jan 22, 2013·18 cites·19 claims
- 0279US7601607B2Protruded contact and insertion of inter-layer-dielectric material to match damascene hardmask to improve undercut for low-k interconnectsCHARTERED SEMICONDUCTOR MFG·Filed 2006·Granted Oct 13, 2009·8 cites·28 claims
- 0378US9443761B2Methods for fabricating integrated circuits having device contactsGLOBALFOUNDRIES SG PTE LTD·Filed 2014·Granted Sep 13, 2016·4 cites·9 claims
- 0466US9449834B2Method of fabricating semiconductor devices including PMOS devices having embedded SiGeWEI QINGSONG·Filed 2011·Granted Sep 20, 2016·2 cites·21 claims
- 0559US7012022B2Self-patterning of photo-active dielectric materials for interconnect isolationCHARTERED SEMICONDUCTOR MFG·Filed 2003·Granted Mar 14, 2006·7 cites·34 claims
- 0657US8018061B2Integrated circuit hard mask processing systemGLOBALFOUNDRIES SG PTE LTD·Filed 2009·Granted Sep 13, 2011·0 cites·10 claims
- 0755US7678586B2Structure and method to prevent charge damage from e-beam curing processCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted Mar 16, 2010·0 cites·22 claims
- 0853US7615484B2Integrated circuit manufacturing method using hard maskCHARTERED SEMICONDUCTOR MFG·Filed 2007·Granted Nov 10, 2009·0 cites·10 claims
- 0950US6995087B2Integrated circuit with simultaneous fabrication of dual damascene via and trenchCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Feb 7, 2006·4 cites·20 claims
- 1049US7153766B2Metal barrier cap fabrication by polymer lift-offCHARTERED SEMICONDUCTOR MFG·Filed 2003·Granted Dec 26, 2006·4 cites·20 claims
- 1149US6967156B2Method to fabricate aligned dual damascene openingsCHARTERED SEMICONDUCTOR MFG·Filed 2003·Granted Nov 22, 2005·3 cites·32 claims
- 1247US7256136B2Self-patterning of photo-active dielectric materials for interconnect isolationCHARTERED SEMICONDUCTOR MFG·Filed 2006·Granted Aug 14, 2007·0 cites·22 claims
- 1346US7372156B2Method to fabricate aligned dual damascene openingsCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted May 13, 2008·0 cites·17 claims
- 1446US7276440B2Method of fabrication of a die oxide ringCHARTERED SEMICONDUCTOR MFG·Filed 2003·Granted Oct 2, 2007·2 cites·7 claims
- 1545US7323408B2Metal barrier cap fabrication by polymer lift-offCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted Jan 29, 2008·0 cites·17 claims
- 1644US7906426B2Method of controlled low-k via etch for Cu interconnectionsGLOBALFOUNDRIES SG PTE LTD·Filed 2007·Granted Mar 15, 2011·0 cites·17 claims
- 1744US2008230907A1Integrated circuit system with carbon enhancementCHARTERED SEMICONDUCTOR MFG·Filed 2007·Application pending·0 cites
- 1843US2005191851A1Barrier metal cap structure on copper lines and viasCHARTERED SEMICONDUCTOR MFG·Filed 2005·Application pending·0 cites
- 1942US2010109155A1Reliable interconnect integrationCHARTERED SEMICONDUCTOR MFG·Filed 2008·Application pending·0 cites
- 2037US2004048468A1Barrier metal cap structure on copper lines and viasCHARTERED SEMICONDUCTOR MFG·Filed 2002·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →