Inventor · disambiguated record
Xiaolong Fei
Also filed as: FEI XIAOLONG
10 granted patents·1 pending application·3 citations·filing 2016–2020
77Inventor score
Files withSHANGHAI ZHAOXIN SEMICONDUCTOR CO LTD6VIA ALLIANCE SEMICONDUCTOR CO LTD3HUAXIA GENERAL PROCESSOR TECH INC2
Top patents by PatentIndex Score
11 records- 0173US11113069B1Implementing quick-release VLV memory access arrayHUAXIA GENERAL PROCESSOR TECH INC·Filed 2020·Granted Sep 7, 2021·1 cites·7 claims
- 0272US10203957B2Processor with improved alias queue and store collision detection to reduce memory violations and load replaysVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2016·Granted Feb 12, 2019·2 cites·20 claims
- 0348US10853080B2System and method of merging partial write results for resolving renaming size issuesSHANGHAI ZHAOXIN SEMICONDUCTOR CO LTD·Filed 2017·Granted Dec 1, 2020·0 cites·20 claims
- 0446US10747542B2Load store dependency predictor using separate alias tables for store address instructions and store data instructionsSHANGHAI ZHAOXIN SEMICONDUCTOR CO LTD·Filed 2018·Granted Aug 18, 2020·0 cites·20 claims
- 0546US10705851B2Scheduling that determines whether to remove a dependent micro-instruction from a reservation station queue based on determining cache hit/miss status of one ore more load micro-instructions once a count reaches a predetermined valueSHANGHAI ZHAOXIN SEMICONDUCTOR CO LTD·Filed 2018·Granted Jul 7, 2020·0 cites·14 claims
- 0646US10509655B1Processor circuit and operation method thereofSHANGHAI ZHAOXIN SEMICONDUCTOR CO LTD·Filed 2018·Granted Dec 17, 2019·0 cites·20 claims
- 0743US10860327B2Methods for scheduling that determine whether to remove a dependent micro-instruction from a reservation station queue based on determining a cache hit/miss status of a load micro-instruction once a count reaches a predetermined value and an apparatus using the sameSHANGHAI ZHAOXIN SEMICONDUCTOR CO LTD·Filed 2018·Granted Dec 8, 2020·0 cites·20 claims
- 0840US10042646B2System and method of merging partial write result during retire phaseVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2016·Granted Aug 7, 2018·0 cites·20 claims
- 0939US10248425B2Processor with slave free list that handles overflow of recycled physical registers and method of recycling physical registers in a processor using a slave free listVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2016·Granted Apr 2, 2019·0 cites·16 claims
- 1038US10776116B2Instruction translation circuit, processor circuit and executing method thereofSHANGHAI ZHAOXIN SEMICONDUCTOR CO LTD·Filed 2018·Granted Sep 15, 2020·0 cites·18 claims
- 1138US2021374068A1Address Fine-Tuning Acceleration SystemHUAXIA GENERAL PROCESSOR TECH INC·Filed 2020·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →