Inventor · disambiguated record
Xiaoying Guo
Also filed as: GUO XIAOYING
21 granted patents·51 pending applications·10 citations·filing 2011–2025
90Inventor score
Files withINTEL CORP65TCL CHINA STAR OPTOELECTRONICS TECH CO LTD2BEIJING XIAOMI MOBILE SOFTWARE CO LTD1DOW GLOBAL TECHNOLOGIES LLC1SHAN BOHAN1
Top patents by PatentIndex Score
72 records- 0195US11990427B2Chiplet first architecture for die tiling applicationsINTEL CORP·Filed 2022·Granted May 21, 2024·2 cites·15 claims
- 0295US11973041B2Chiplet first architecture for die tiling applicationsINTEL CORP·Filed 2021·Granted Apr 30, 2024·2 cites·41 claims
- 0391US11881182B1Light-emitting device driver chip, backlight module, and display panelTCL CHINA STAR OPTOELECTRONICS TECH CO LTD·Filed 2022·Granted Jan 23, 2024·2 cites·14 claims
- 0485US12308329B2Chiplet first architecture for die tiling applicationsINTEL CORP·Filed 2024·Granted May 20, 2025·0 cites·20 claims
- 0584US11088103B2First layer interconnect first on carrier approach for EMIB patchINTEL CORP·Filed 2018·Granted Aug 10, 2021·3 cites·20 claims
- 0683US2025253265A1Chiplet first architecture for die tiling applicationsINTEL CORP·Filed 2025·Application pending·0 cites
- 0776US12354992B2First layer interconnect first on carrier approach for EMIB patchINTEL CORP·Filed 2022·Granted Jul 8, 2025·0 cites·16 claims
- 0875US11769735B2Chiplet first architecture for die tiling applicationsINTEL CORP·Filed 2019·Granted Sep 26, 2023·1 cites·25 claims
- 0970US12456705B2First layer interconnect first on carrier approach for EMIB patchINTEL CORP·Filed 2021·Granted Oct 28, 2025·0 cites·18 claims
- 1060US2013011697A1High efficiency microbial fuel cellDOW GLOBAL TECHNOLOGIES LLC·Filed 2011·Application pending·0 cites
- 1158US12341117B2Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substratesINTEL CORP·Filed 2021·Granted Jun 24, 2025·0 cites·25 claims
- 1258US2025218998A1Low temperature solder interconnect for package pitch scalingINTEL CORP·Filed 2023·Application pending·0 cites
- 1357US12354883B2Omni directional interconnect with magnetic fillers in mold matrixINTEL CORP·Filed 2021·Granted Jul 8, 2025·0 cites·18 claims
- 1457US2025219028A1Deep trench capacitors in multi-core integrated circuit device package substratesINTEL CORP·Filed 2023·Application pending·0 cites
- 1557US2025210426A1Microelectronic assemblies with strengthened glass coresINTEL CORP·Filed 2023·Application pending·0 cites
- 1657US2025220818A1Flow enhanced dummy structure to enable capillary flow based sidewall fillingINTEL CORP·Filed 2023·Application pending·0 cites
- 1757US2025218880A1Microelectronic assemblies with pillar-first conductive via formation in glass coresINTEL CORP·Filed 2023·Application pending·0 cites
- 1857US2025218926A1Microelectronic assemblies including cavity-less encapsulated diesINTEL CORP·Filed 2023·Application pending·0 cites
- 1956US2025273607A1Methods and architectures for shallow fiducial and metal defined pad designsINTEL CORP·Filed 2024·Application pending·0 cites
- 2056US2025112085A1Apparatus and methods for capillary underfill of embedded devicesINTEL CORP·Filed 2023·Application pending·0 cites
- 2156US2025183180A1Direct bonding for embedded bridges with viasINTEL CORP·Filed 2023·Application pending·0 cites
- 2256US2025218957A1Methods and apparatus to embed a semiconductor device in a glass coreINTEL CORP·Filed 2023·Application pending·0 cites
- 2355US2025106983A1Stiffener architectures for glass edge protectionINTEL CORP·Filed 2023·Application pending·0 cites
- 2455US2025192069A1Microelectronic assemblies with pre-singulation edge features in glass coresINTEL CORP·Filed 2023·Application pending·0 cites
- 2555US2025112164A1Controlling substrate bump heightINTEL CORP·Filed 2023·Application pending·0 cites
- 2655US2025192070A1Microelectronic assemblies with post-singulation edge features in glass coresINTEL CORP·Filed 2023·Application pending·0 cites
- 2754US2024222301A1Methods and apparatus for optical thermal treatment in semiconductor packagesINTEL CORP·Filed 2022·Application pending·0 cites
- 2854US2024222136A1Electrical layer with roughened surfacesINTEL CORP·Filed 2022·Application pending·0 cites
- 2954US2024312865A1Methods, systems, apparatus, and articles of manufacture to improve reliability of vias in a glass substrate of an integrated circuit packageINTEL CORP·Filed 2023·Application pending·0 cites
- 3054US2024332125A12d fillers for reduced cte for pidINTEL CORP·Filed 2023·Application pending·0 cites
- 3153US12334422B2Methods and apparatus to reduce defects in interconnects between semicondcutor dies and package substratesINTEL CORP·Filed 2021·Granted Jun 17, 2025·0 cites·24 claims
- 3253US2024213116A1Methods, systems, apparatus, and articles of manufacture to cool integrated circuit packages having glass substratesINTEL CORP·Filed 2022·Application pending·0 cites
- 3353US2024213169A1Low die height glass substrate device and methodINTEL CORP·Filed 2022·Application pending·0 cites
- 3453US2024222210A1Glass substrate fabrication using hybrid bondingINTEL CORP·Filed 2022·Application pending·0 cites
- 3553US2024222238A1Apparatus and method for attaching an optical component using no remelt metallurgyINTEL CORP·Filed 2022·Application pending·0 cites
- 3653US2024219660A1Optical semiconductor package and methodINTEL CORP·Filed 2022·Application pending·0 cites
- 3753US2024222345A1Die attach in glass core package through organic-to-organic bondingINTEL CORP·Filed 2022·Application pending·0 cites
- 3853US2024112971A1Singulation of integrated circuit package substrates with glass coresINTEL CORP·Filed 2022·Application pending·0 cites
- 3953US2024222243A1Apparatus and method for attaching an optical component using hybrid bondingINTEL CORP·Filed 2022·Application pending·0 cites
- 4053US2024222304A1Methods and apparatus to reduce solder bump bridging between two substratesINTEL CORP·Filed 2022·Application pending·0 cites
- 4153US2025192059A1Embedded bridge with through silicon via bonding architecturesINTEL CORP·Filed 2023·Application pending·0 cites
- 4253US2025006645A1Microelectronic assemblies including a photoimageable dielectric for hybrid bonding and die encapsulationINTEL CORP·Filed 2023·Application pending·0 cites
- 4353US2024219655A1Optical semiconductor package and methodINTEL CORP·Filed 2022·Application pending·0 cites
- 4453US2024222257A1Glass substrate device with plated through holesINTEL CORP·Filed 2022·Application pending·0 cites
- 4553US2025112136A1Glass core protection using peripheral buffer layersINTEL CORP·Filed 2023·Application pending·0 cites
- 4653US2024213170A1Glass substrate device with embedded componentsINTEL CORP·Filed 2022·Application pending·0 cites
- 4753US2024203806A1Glass layer with litho defined through-glass viaINTEL CORP·Filed 2022·Application pending·0 cites
- 4853US2024215269A1Glass substrate device with through glass cavityINTEL CORP·Filed 2022·Application pending·0 cites
- 4953US2024186227A1Integrated circuit package architectures with core and/or build-up layers comprising spin-on glass (sog)INTEL CORP·Filed 2022·Application pending·0 cites
- 5052US12512397B2Substrates having adhesion promotor layers and related methodsTHE INTEL CORP·Filed 2022·Granted Dec 30, 2025·0 cites·20 claims
Showing the top 50 of 72 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →