Inventor · disambiguated record
Yannick Marc Nevers
Also filed as: NEVERS YANNICK MARC
5 granted patents·2 pending applications·21 citations·filing 2009–2023
75Inventor score
Top patents by PatentIndex Score
7 records- 0177US8422262B2Generating ROM bit cell arraysNEVERS YANNICK MARC·Filed 2011·Granted Apr 16, 2013·9 cites·5 claims
- 0265US7961490B2Generating ROM bit cell arraysADVANCED RISC MACH LTD·Filed 2009·Granted Jun 14, 2011·6 cites·12 claims
- 0361US7936578B2Read only memory cell for storing a multiple bit valueADVANCED RISC MACH LTD·Filed 2009·Granted May 3, 2011·5 cites·19 claims
- 0449US8941428B2Low power latching circuitsADVANCED RISC MACH LTD·Filed 2014·Granted Jan 27, 2015·1 cites·15 claims
- 0540US10558585B2Dynamic memory scramblingADVANCED RISC MACH LTD·Filed 2016·Granted Feb 11, 2020·0 cites·20 claims
- 0640US2024249790A1Register Bank Architecture with LatchesADVANCED RISC MACH LTD·Filed 2023·Application pending·0 cites
- 0732US2014125392A1Low power latching circuitsADVANCED RISC MACH LTD·Filed 2012·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →