Inventor · disambiguated record
Yasuyuki Sekimoto
Also filed as: SEKIMOTO YASUYUKI
6 granted patents·1 pending application·8 citations·filing 2009–2018
73Inventor score
Top patents by PatentIndex Score
7 records- 0165US8570763B2Method of forming hole for interlayer connection conductor, method of producing resin substrate and component-incorporated substrate, and resin substrate and component-incorporated substrateSEKIMOTO YASUYUKI·Filed 2009·Granted Oct 29, 2013·4 cites·6 claims
- 0259US8419884B2Method for manufacturing multilayer wiring substrateSEKIMOTO YASUYUKI·Filed 2010·Granted Apr 16, 2013·2 cites·7 claims
- 0358US10090268B2Method of forming solder bump, and solder bumpMURATA MANUFACTURING CO·Filed 2015·Granted Oct 2, 2018·1 cites·16 claims
- 0458US8794499B2Method for manufacturing substrateSEKIMOTO YASUYUKI·Filed 2011·Granted Aug 5, 2014·1 cites·6 claims
- 0545US10522289B2Electronic component and electronic component series including the sameMURATA MANUFACTURING CO·Filed 2016·Granted Dec 31, 2019·0 cites·20 claims
- 0644US10111325B2Elastic conductorMURATA MANUFACTURING CO·Filed 2018·Granted Oct 23, 2018·0 cites·19 claims
- 0742US2012321814A1Method of forming hole for interlayer connection conductor, method of producing resin substrate and component-incorporated substrate, and resin substrate and component-incorporated substrateSEKIMOTO YASUYUKI·Filed 2012·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →