Inventor · disambiguated record
Yeow Kheng Lim
Also filed as: LIM YEOW KHENG
25 granted patents·3 pending applications·365 citations·filing 2000–2016
96Inventor score
Files withCHARTERED SEMICONDUCTOR MFG15GLOBALFOUNDRIES SG PTE LTD3TAN JUAN BOON3LIM YEOW KHENG2CHARTERED SEMICONDUCTOR MANFAC1
Top patents by PatentIndex Score
28 records- 0192US8358007B2Integrated circuit system employing low-k dielectrics and method of manufacture thereofGLOBALFOUNDRIES SG PTE LTD·Filed 2010·Granted Jan 22, 2013·18 cites·19 claims
- 0289US6380084B1Method to form high performance copper damascene interconnects by de-coupling via and metal line fillingCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Apr 30, 2002·59 cites·33 claims
- 0389US6319767B1Method to eliminate top metal corner shaping during bottom metal patterning for MIM capacitors via plasma ashing and hard masking techniqueCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Nov 20, 2001·50 cites·29 claims
- 0486US8466062B2TSV backside processing using copper damascene interconnect technologyLU YUE KANG·Filed 2011·Granted Jun 18, 2013·20 cites·32 claims
- 0586US6355563B1Versatile copper-wiring layout design with low-k dielectric integrationCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Mar 12, 2002·46 cites·33 claims
- 0685US7790617B2Formation of metal silicide layer over copper interconnect for reliability enhancementCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted Sep 7, 2010·11 cites·29 claims
- 0783US6558994B2Dual silicon-on-insulator device wafer dieCHARTERED SEMICONDUCTORS MAUFA·Filed 2001·Granted May 6, 2003·36 cites·13 claims
- 0882US7253097B2Integrated circuit system using dual damascene processCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted Aug 7, 2007·11 cites·20 claims
- 0981US8759947B2Back-side MOM/MIM devicesTAN JUAN BOON·Filed 2012·Granted Jun 24, 2014·8 cites·18 claims
- 1079US6613652B2Method for fabricating SOI devices with option of incorporating air-gap feature for better insulation and performanceCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Sep 2, 2003·28 cites·33 claims
- 1171US8716856B2Device with integrated power supplyTAN JUAN BOON·Filed 2012·Granted May 6, 2014·3 cites·20 claims
- 1270US6432797B1Simplified method to reduce or eliminate STI oxide divotsCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Aug 13, 2002·13 cites·31 claims
- 1366US6468880B1Method for fabricating complementary silicon on insulator devices using wafer bondingCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Oct 22, 2002·14 cites·14 claims
- 1465US6780691B2Method to fabricate elevated source/drain transistor with large area for silicidationCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Aug 24, 2004·12 cites·37 claims
- 1563US8860185B2Crack-arresting structure for through-silicon viasYUAN SHAONING·Filed 2012·Granted Oct 14, 2014·3 cites·15 claims
- 1660US7119010B2Integrated circuit with self-aligned line and via and manufacturing method thereforCHARTERED SEMICONDUCTOR MANFAC·Filed 2002·Granted Oct 10, 2006·10 cites·9 claims
- 1758US6518133B1Method for fabricating a small dimensional gate with elevated source/drain structuresCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Feb 11, 2003·8 cites·21 claims
- 1857US6849928B2Dual silicon-on-insulator device wafer dieCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Feb 1, 2005·6 cites·10 claims
- 1956US8766454B2Integrated circuit with self-aligned line and viaLIM YEOW KHENG·Filed 2006·Granted Jul 1, 2014·1 cites·10 claims
- 2051US6399471B1Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron applicationCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Jun 4, 2002·4 cites·7 claims
- 2149US8957523B2Dielectric posts in metal layersGLOBALFOUNDRIES SG PTE LTD·Filed 2013·Granted Feb 17, 2015·0 cites·20 claims
- 2249US6967156B2Method to fabricate aligned dual damascene openingsCHARTERED SEMICONDUCTOR MFG·Filed 2003·Granted Nov 22, 2005·3 cites·32 claims
- 2348US2016233157A1Slot designs in wide metal linesGLOBALFOUNDRIES SG PTE LTD·Filed 2016·Application pending·0 cites
- 2446US7372156B2Method to fabricate aligned dual damascene openingsCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted May 13, 2008·0 cites·17 claims
- 2544US9318378B2Slot designs in wide metal linesLIM YEOW KHENG·Filed 2004·Granted Apr 19, 2016·1 cites·18 claims
- 2639US6472697B2Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron applicationCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Oct 29, 2002·0 cites·5 claims
- 2738US2014264733A1Device with integrated passive componentGLOBALFOUNDERIES SINGAPORE PTE LTD·Filed 2013·Application pending·0 cites
- 2835US2013277810A1Method for forming heat sink with through silicon viasTAN JUAN BOON·Filed 2012·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →