Inventor · disambiguated record
Yeshayahu Mor
Also filed as: MOR YESHAYAHU
16 granted patents·1 pending application·460 citations·filing 1980–2002
95Inventor score
Files withINTEGRATED DEVICE TECH6PERFORMANCE SEMICONDUCTOR CORP5FAIRCHILD CAMERA INSTR CO3CORESMA LTD1FAIRCHILD CAMERA AND INSTR1
Top patents by PatentIndex Score
17 records- 0176US5317711AStructure and method for monitoring an internal cacheINTEGRATED DEVICE TECH·Filed 1991·Granted May 31, 1994·75 cites·14 claims
- 0275US4713750AMicroprocessor with compact mapped programmable logic arrayFAIRCHILD CAMERA INSTR CO·Filed 1984·Granted Dec 15, 1987·50 cites·6 claims
- 0374US4905178AFast shifter method and structurePERFORMANCE SEMICONDUCTOR CORP·Filed 1986·Granted Feb 27, 1990·56 cites·21 claims
- 0473US4884231AMicroprocessor system with extended arithmetic logic unitPERFORMANCE SEMICONDUCTOR CORP·Filed 1986·Granted Nov 28, 1989·53 cites·3 claims
- 0571US6687757B1Packet processorFLEXTRONICS SEMICONDUCTOR INC·Filed 2000·Granted Feb 3, 2004·25 cites·36 claims
- 0671US5636363AHardware control structure and method for off-chip monitoring entries of an on-chip cacheINTEGRATED DEVICE TECH·Filed 1991·Granted Jun 3, 1997·57 cites·4 claims
- 0764US4755962AMicroprocessor having multiplication circuitry implementing a modified Booth algorithmFAIRCHILD CAMERA AND INSTR·Filed 1987·Granted Jul 5, 1988·37 cites·2 claims
- 0854US4396979AMicroprocessor with improved arithmetic logic unit data pathFAIRCHILD CAMERA INSTR CO·Filed 1980·Granted Aug 2, 1983·21 cites·3 claims
- 0949US5386579AMinimum pin-count multiplexed address/data bus with byte enable and burst address counter support microprocessor transmitting byte enable signals on multiplexed address/data bus having burst address counter for supporting signal datum and burst transferINTEGRATED DEVICE TECH·Filed 1991·Granted Jan 31, 1995·25 cites·14 claims
- 1045US4412283AHigh performance microprocessor systemFAIRCHILD CAMERA INSTR CO·Filed 1980·Granted Oct 25, 1983·15 cites·9 claims
- 1143US5649232AStructure and method for multiple-level read buffer supporting optimal throttled read operations by regulating transfer rateINTEGRATED DEVICE TECH·Filed 1995·Granted Jul 15, 1997·17 cites·14 claims
- 1242US2002176416A1Packet processorCORESMA LTD·Filed 2002·Application pending·0 cites
- 1335US5517659AMultiplexed status and diagnostic pins in a microprocessor with on-chip cachesINTEGRATED DEVICE TECH·Filed 1994·Granted May 14, 1996·8 cites·8 claims
- 1434US5894176AFlexible reset scheme supporting normal system operation, test and emulation modesINTEGRATED DEVICE TECH·Filed 1994·Granted Apr 13, 1999·5 cites·9 claims
- 1533US4811211AOn-line overflow response system and ALU branching structurePERFORMANCE SEMICONDUCTOR CORP·Filed 1986·Granted Mar 7, 1989·7 cites·12 claims
- 1631US4858166AMethod and structure for performing floating point comparisonPERFORMANCE SEMICONDUCTOR CORP·Filed 1986·Granted Aug 15, 1989·6 cites·1 claims
- 1728US4807124ARegister addressing system for efficient microroutine sharing and optimizationPERFORMANCE SEMICONDUCTOR CORP·Filed 1986·Granted Feb 21, 1989·3 cites·9 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →