Inventor · disambiguated record
Yelehanka Ramachandramurthy Pradeep
Also filed as: PRADEEP YELEHANKA · PRADEEP YELEHANKA R · PRADEEP YELEHANKA RAMACHANDRAM · PRADEEP YELEHANKA RAMACHANDRAMURTHY
59 granted patents·4 pending applications·2,253 citations·filing 1997–2015
99Inventor score
Top patents by PatentIndex Score
63 records- 0197US6300177B1Method to form transistors with multiple threshold voltages (VT) using a combination of different work function gate materialsCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Oct 9, 2001·175 cites·26 claims
- 0296US6461900B1Method to form a self-aligned CMOS inverter using vertical device integrationCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Oct 8, 2002·141 cites·22 claims
- 0394US6313008B1Method to form a balloon shaped STI using a micro machining technique to remove heavily doped siliconCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Nov 6, 2001·90 cites·30 claims
- 0493US6277683B1Method of forming a sidewall spacer and a salicide blocking shape, using only one silicon nitride layerCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Aug 21, 2001·98 cites·25 claims
- 0592US6337262B1Self aligned T-top gate process integrationCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Jan 8, 2002·90 cites·5 claims
- 0691US6406945B1Method for forming a transistor gate dielectric with high-K and low-K regionsCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Jun 18, 2002·59 cites·17 claims
- 0791US6403485B1Method to form a low parasitic capacitance pseudo-SOI CMOS deviceCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Jun 11, 2002·66 cites·27 claims
- 0889US6417056B1Method to form low-overlap-capacitance transistors by forming microtrench at the gate edgeCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Jul 9, 2002·51 cites·27 claims
- 0989US6306715B1Method to form smaller channel with CMOS device by isotropic etching of the gate materialsCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Oct 23, 2001·46 cites·14 claims
- 1089US6303447B1Method for forming an extended metal gate using a damascene processCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Oct 16, 2001·51 cites·21 claims
- 1188US6716693B1Method of forming a surface coating layer within an opening within a body by atomic layer depositionCHARTERED SEMICONDUCTOR MFG·Filed 2003·Granted Apr 6, 2004·49 cites·28 claims
- 1288US6511884B1Method to form and/or isolate vertical transistorsCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Jan 28, 2003·48 cites·27 claims
- 1388US6468877B1Method to form an air-gap under the edges of a gate electrode by using disposable spacer/linerCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Oct 22, 2002·53 cites·21 claims
- 1488US6277700B1High selective nitride spacer etch with high ratio of spacer width to deposited nitride thicknessCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Aug 21, 2001·52 cites·17 claims
- 1587US6468853B1Method of fabricating a shallow trench isolation structure with reduced local oxide recess near cornerCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Oct 22, 2002·83 cites·46 claims
- 1687US6436770B1Method to control the channel length of a vertical transistor by first forming channel using selective epi and source/drain using implantationCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Aug 20, 2002·45 cites·19 claims
- 1787US6355581B1Gas-phase additives for an enhancement of lateral etch component during high density plasma film deposition to improve film gap-fill capabilityCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Mar 12, 2002·52 cites·17 claims
- 1887US6316304B1Method of forming spacers of multiple widthsCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Nov 13, 2001·60 cites·27 claims
- 1986US6346468B1Method for forming an L-shaped spacer using a disposable polysilicon spacerCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Feb 12, 2002·39 cites·6 claims
- 2085US6399448B1Method for forming dual gate oxideCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Jun 4, 2002·67 cites·12 claims
- 2183US6709934B2Method for forming variable-K gate dielectricCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Mar 23, 2004·26 cites·10 claims
- 2283US6451704B1Method for forming PLDD structure with minimized lateral dopant diffusionCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Sep 17, 2002·59 cites·44 claims
- 2383US6248006B1CMP uniformityCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Jun 19, 2001·27 cites·7 claims
- 2481US6284613B1Method for forming a T-gate for better salicidationCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Sep 4, 2001·61 cites·10 claims
- 2581US6228770B1Method to form self-sealing air gaps between metal interconnectsCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted May 8, 2001·35 cites·20 claims
- 2681US5866448AProcedure for forming a lightly-doped-drain structure using polymer layerCHARTERED SEMICONDUCTOR MFG·Filed 1997·Granted Feb 2, 1999·58 cites·29 claims
- 2779US6300251B1Repeatable end point method for anisotropic etch of inorganic buried anti-reflective coating layer over siliconCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Oct 9, 2001·29 cites·31 claims
- 2879US6251764B1Method to form an L-shaped silicon nitride sidewall spacerCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Jun 26, 2001·60 cites·20 claims
- 2979US6211008B1Method for forming high-density high-capacity capacitorCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Apr 3, 2001·27 cites·20 claims
- 3078US6228713B1Self-aligned floating gate for memory application using shallow trench isolationCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted May 8, 2001·64 cites·15 claims
- 3178US6156598AMethod for forming a lightly doped source and drain structure using an L-shaped spacerCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Dec 5, 2000·51 cites·15 claims
- 3276US6455377B1Method to form very high mobility vertical channel transistor by selective deposition of SiGe or multi-quantum wells (MQWs)CHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Sep 24, 2002·21 cites·35 claims
- 3376US6387765B2Method for forming an extended metal gate using a damascene processCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted May 14, 2002·19 cites·11 claims
- 3474US6566208B2Method to form elevated source/drain using poly spacerCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted May 20, 2003·22 cites·19 claims
- 3572US6461887B1Method to form an inverted staircase STI structure by etch-deposition-etch and selective epitaxial growthCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Oct 8, 2002·18 cites·21 claims
- 3672US6380088B1Method to form a recessed source drain on a trench side wall with a replacement gate techniqueCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Apr 30, 2002·19 cites·29 claims
- 3771US7382027B2MOSFET device with low gate contact resistanceCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted Jun 3, 2008·4 cites·23 claims
- 3871US5858847AMethod for a lightly doped drain structureCHARTERED SEMICONDUCTOR MFG·Filed 1997·Granted Jan 12, 1999·44 cites·13 claims
- 3969US6303449B1Method to form self-aligned elevated source/drain by selective removal of gate dielectric in the source/drain region followed by poly deposition and CMPCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Oct 16, 2001·12 cites·11 claims
- 4068US6632745B1Method of forming almost L-shaped spacer for improved ILD gap fillCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Oct 14, 2003·20 cites·45 claims
- 4164US6861317B1Method of making direct contact on gate by using dielectric stop layerCHARTERED SEMICONDUCTOR MFG·Filed 2003·Granted Mar 1, 2005·10 cites·16 claims
- 4264US6852605B2Method of forming an inductor with continuous metal depositionCHARTERED SEMICONDUCTOR MFG·Filed 2003·Granted Feb 8, 2005·10 cites·17 claims
- 4364US6544824B1Method to form a vertical transistor by first forming a gate/spacer stack, then using selective epitaxy to form source, drain and channelCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Apr 8, 2003·12 cites·26 claims
- 4463US6200887B1Method to form a smooth gate polysilicon sidewall in the fabrication of integrated circuitsCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Mar 13, 2001·10 cites·23 claims
- 4562US8293545B2Critical dimension for trench and viasCONG HAI·Filed 2007·Granted Oct 23, 2012·3 cites·22 claims
- 4662US6436774B1Method for forming variable-K gate dielectricCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Aug 20, 2002·8 cites·10 claims
- 4759US6294480B1Method for forming an L-shaped spacer with a disposable organic top coatingCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Sep 25, 2001·24 cites·17 claims
- 4858US6541327B1Method to form self-aligned source/drain CMOS device on insulated staircase oxideCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Apr 1, 2003·8 cites·9 claims
- 4958US6312999B1Method for forming PLDD structure with minimized lateral dopant diffusionCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Nov 6, 2001·13 cites·20 claims
- 5056US6660642B2Toxic residual gas removal by non-reactive ion sputteringCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Dec 9, 2003·7 cites·24 claims
Showing the top 50 of 63 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →