Inventor · disambiguated record
Yogananda Rao Chillariga
Also filed as: CHILLARIGA YOGANANDA RAO
6 granted patents·2 pending applications·4 citations·filing 2007–2023
68Inventor score
Top patents by PatentIndex Score
8 records- 0165US12430199B2Flow control between peripheral component interconnect express devicesQUALCOMM INC·Filed 2022·Granted Sep 30, 2025·0 cites·22 claims
- 0265US12282392B2Interconnects between chiplets and related link initialization protocolsQUALCOMM INC·Filed 2023·Granted Apr 22, 2025·0 cites·30 claims
- 0363US8000751B2Method for providing calling party selectable ring tones in a wireless communications networkALCATEL LUCENT·Filed 2007·Granted Aug 16, 2011·4 cites·20 claims
- 0460US12197775B2Memory devices write buffer managementQUALCOMM INC·Filed 2023·Granted Jan 14, 2025·0 cites·27 claims
- 0560US12153527B2Data rate increase for faulty lane recovery in multiple lane data linksQUALCOMM INC·Filed 2022·Granted Nov 26, 2024·0 cites·24 claims
- 0658US12056364B1Write buffer and logical unit management in a data storage deviceQUALCOMM INC·Filed 2023·Granted Aug 6, 2024·0 cites·25 claims
- 0750US2024264965A1Channel direction management for bus interfacesQUALCOMM INC·Filed 2023·Application pending·0 cites
- 0834US2020241625A1Transitioning universal flash storage (ufs) gears during a clock gate/hibernation delayQUALCOMM INC·Filed 2019·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →