Inventor · disambiguated record
Younsung Choi
Also filed as: CHOI YOUNSUNG
13 granted patents·3 pending applications·8 citations·filing 2010–2020
85Inventor score
Top patents by PatentIndex Score
16 records- 0186US9812452B2Method to form silicide and contact at embedded epitaxial facetTEXAS INSTRUMENTS INC·Filed 2016·Granted Nov 7, 2017·4 cites·17 claims
- 0274US10026837B2Embedded SiGe process for multi-threshold PMOS transistorsTEXAS INSTRUMENTS INC·Filed 2015·Granted Jul 17, 2018·2 cites·11 claims
- 0370US9735159B2Optimized layout for relaxed and strained liner in single stress liner technologyTEXAS INSTRUMENTS INC·Filed 2014·Granted Aug 15, 2017·2 cites·20 claims
- 0467US11251093B2Poly gate extension design methodology to improve CMOS performance in dual stress liner process flowTEXAS INSTRUMENTS INC·Filed 2020·Granted Feb 15, 2022·0 cites·18 claims
- 0559US10734290B2Poly gate extension design methodology to improve CMOS performance in dual stress liner process flowTEXAS INSTRUMENTS INC·Filed 2018·Granted Aug 4, 2020·0 cites·17 claims
- 0657US9508601B2Method to form silicide and contact at embedded epitaxial facetTEXAS INSTRUMENTS INC·Filed 2014·Granted Nov 29, 2016·0 cites·19 claims
- 0755US10008499B2Method to form silicide and contact at embedded epitaxial facetTEXAS INSTRUMENTS INC·Filed 2017·Granted Jun 26, 2018·0 cites·17 claims
- 0854US10134643B2Poly gate extension design methodology to improve CMOS performance in dual stress liner process flowTEXAS INSTRUMENTS INC·Filed 2017·Granted Nov 20, 2018·0 cites·11 claims
- 0954US9583488B2Poly gate extension design methodology to improve CMOS performance in dual stress liner process flowTEXAS INSTRUMENTS INC·Filed 2014·Granted Feb 28, 2017·0 cites·8 claims
- 1054US9496142B2Dummy gate placement methodology to enhance integrated circuit performanceTEXAS INSTRUMENTS INC·Filed 2014·Granted Nov 15, 2016·0 cites·17 claims
- 1151US9947765B2Dummy gate placement methodology to enhance integrated circuit performanceTEXAS INSTRUMENTS INC·Filed 2016·Granted Apr 17, 2018·0 cites·10 claims
- 1251US2018308977A1Embedded sige process for multi-threshold pmos transistorsTEXAS INSTRUMENTS INC·Filed 2018·Application pending·0 cites
- 1345US2015187656A1Laser anneals for reduced diode leakageTEXAS INSTRUMENTS INC·Filed 2014·Application pending·0 cites
- 1442US8438526B2Method for minimizing transistor and analog component variation in CMOS processes through design rule restrictionsBALDWIN GREGORY CHARLES·Filed 2010·Granted May 7, 2013·0 cites·15 claims
- 1535US10559469B2Dual pocket approach in PFETs with embedded SI-GE source/drainTEXAS INSTRUMENTS INC·Filed 2015·Granted Feb 11, 2020·0 cites·7 claims
- 1634US2016172443A1Method and apparatus to tune threshold voltage of device with high angle source/drain implantsTEXAS INSTRUMENTS INC·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →