Inventor · disambiguated record
Yoshiyuki Miyayama
Also filed as: MIYAYAMA YOSHIYUKI
51 granted patents·2,055 citations·filing 1992–2008
99Inventor score
Technology areasG06F
Top patents by PatentIndex Score
51 records- 0195US7739482B2High-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 2006·Granted Jun 15, 2010·26 cites·18 claims
- 0295US5560032AHigh-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distributionSEIKO EPSON CORP·Filed 1995·Granted Sep 24, 1996·193 cites·29 claims
- 0395US5539911AHigh-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 1992·Granted Jul 23, 1996·133 cites·56 claims
- 0495US5438668ASystem and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computerSEIKO EPSON CORP·Filed 1992·Granted Aug 1, 1995·159 cites·29 claims
- 0592US6647485B2High-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 2001·Granted Nov 11, 2003·42 cites·40 claims
- 0691US5689720AHigh-performance superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 1996·Granted Nov 18, 1997·90 cites·11 claims
- 0790US6965987B2System and method for handling load and/or store operations in a superscalar microprocessorSEIKO EPSON CORP·Filed 2003·Granted Nov 15, 2005·43 cites·58 claims
- 0890US5619666ASystem for translating non-native instructions to native instructions and combining them into a final bucket for processing on a host processorSEIKO EPSON CORP·Filed 1995·Granted Apr 8, 1997·110 cites·12 claims
- 0989US6986024B2High-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 2002·Granted Jan 10, 2006·28 cites·24 claims
- 1088US6915412B2High-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 2002·Granted Jul 5, 2005·25 cites·26 claims
- 1187US6948052B2High-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 2002·Granted Sep 20, 2005·23 cites·39 claims
- 1287US5961629AHigh performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 1998·Granted Oct 5, 1999·135 cites·27 claims
- 1387US5546552AMethod for translating non-native instructions to native instructions and combining them into a final bucket for processing on a host processorSEIKO EPSON CORP·Filed 1995·Granted Aug 13, 1996·82 cites·7 claims
- 1486US7721070B2High-performance, superscalar-based computer system with out-of-order instruction executionNGUYEN LE TRONG·Filed 2008·Granted May 18, 2010·10 cites·21 claims
- 1586US7162610B2High-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 2003·Granted Jan 9, 2007·21 cites·35 claims
- 1685US6959375B2High-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 2002·Granted Oct 25, 2005·19 cites·10 claims
- 1784US6934829B2High-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 2003·Granted Aug 23, 2005·17 cites·21 claims
- 1883US6308258B1Data processing circuit with target instruction and prefix instructionSEIKO EPSON CORP·Filed 2000·Granted Oct 23, 2001·32 cites·19 claims
- 1982US6922795B2Microcomputer, electronic equipment, and debugging systemSEIKO EPSON CORP·Filed 2003·Granted Jul 26, 2005·26 cites·2 claims
- 2082US5448705ARISC microprocessor architecture implementing fast trap and exception stateSEIKO EPSON CORP·Filed 1993·Granted Sep 5, 1995·79 cites·3 claims
- 2181US7664935B2System and method for translating non-native instructions to native instructions for processing on a host processorCOON BRETT·Filed 2008·Granted Feb 16, 2010·6 cites·18 claims
- 2280US7555632B2High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distributionSEIKO EPSON CORP·Filed 2005·Granted Jun 30, 2009·6 cites·23 claims
- 2380US6941447B2High-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 2003·Granted Sep 6, 2005·13 cites·23 claims
- 2480US6128723AHigh-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 1999·Granted Oct 3, 2000·42 cites·27 claims
- 2579US7941635B2High-performance superscalar-based computer system with out-of order instruction execution and concurrent results distributionSEIKO EPSON CORP·Filed 2006·Granted May 10, 2011·5 cites·5 claims
- 2679US7028161B2High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distributionSEIKO EPSON CORP·Filed 2001·Granted Apr 11, 2006·17 cites·39 claims
- 2779US6038654AHigh performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 1999·Granted Mar 14, 2000·39 cites·80 claims
- 2879US5481685ARISC microprocessor architecture implementing fast trap and exception stateSEIKO EPSON CORP·Filed 1994·Granted Jan 2, 1996·66 cites·16 claims
- 2978US8019975B2System and method for handling load and/or store operations in a superscalar microprocessorSEIKO EPSON CORP·Filed 2005·Granted Sep 13, 2011·5 cites·59 claims
- 3078US6954847B2System and method for translating non-native instructions to native instructions for processing on a host processorTRANSMETA CORP·Filed 2002·Granted Oct 11, 2005·14 cites·7 claims
- 3177US7343473B2System and method for translating non-native instructions to native instructions for processing on a host processorTRANSMETA CORP·Filed 2005·Granted Mar 11, 2008·4 cites·18 claims
- 3277US6092181AHigh-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 1997·Granted Jul 18, 2000·37 cites·62 claims
- 3376US6272619B1High-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 1999·Granted Aug 7, 2001·34 cites·80 claims
- 3476US6256720B1High performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 1999·Granted Jul 3, 2001·34 cites·80 claims
- 3575US6799157B1Method for improving pin compatibility in microcomputer emulation equipmentSEIKO EPSON CORP·Filed 2000·Granted Sep 28, 2004·21 cites·25 claims
- 3675US6101594AHigh-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 1999·Granted Aug 8, 2000·31 cites·31 claims
- 3774US6282630B1High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distributionSEIKO EPSON CORP·Filed 1999·Granted Aug 28, 2001·41 cites·44 claims
- 3873US6249167B1Semiconductor integrated circuit, semiconductor device, and electronic equipment comprising the sameSEIKO EPSON CORP·Filed 1998·Granted Jun 19, 2001·69 cites·22 claims
- 3973US6038653AHigh-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distributionSEIKO EPSON CORP·Filed 1998·Granted Mar 14, 2000·39 cites·33 claims
- 4071US5832292AHigh-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distributionSEIKO EPSON CORP·Filed 1996·Granted Nov 3, 1998·38 cites·20 claims
- 4170US7487333B2High-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 2003·Granted Feb 3, 2009·6 cites·59 claims
- 4268US6167505AData processing circuit with target instruction and prefix instructionSEIKO EPSON CORP·Filed 1996·Granted Dec 26, 2000·45 cites·9 claims
- 4367US6665821B1Microcomputer, electronic equipment, and debugging systemSEIKO EPSON CORP·Filed 1999·Granted Dec 16, 2003·40 cites·11 claims
- 4465US7065678B2Microcomputer, electronic equipment, and debugging systemSEIKO EPSON CORP·Filed 2004·Granted Jun 20, 2006·8 cites·3 claims
- 4565US5983334ASuperscalar microprocessor for out-of-order and concurrently executing at least two RISC instructions translating from in-order CISC instructionsSEIKO EPSON CORP·Filed 1997·Granted Nov 9, 1999·26 cites·5 claims
- 4653US5987593ASystem and method for handling load and/or store operations in a superscalar microprocessorSEIKO EPSON CORP·Filed 1997·Granted Nov 16, 1999·18 cites·71 claims
- 4748US6263423B1System and method for translating non-native instructions to native instructions for processing on a host processorSEIKO EPSON CORP·Filed 1999·Granted Jul 17, 2001·11 cites·19 claims
- 4846US6560692B1Data processing circuit, microcomputer, and electronic equipmentSEIKO EPSON CORP·Filed 1997·Granted May 6, 2003·18 cites·15 claims
- 4943US6233596B1Multiple sum-of-products circuit and its use in electronic equipment and microcomputersSEIKO EPSON CORP·Filed 1997·Granted May 15, 2001·15 cites·22 claims
- 5039US5297287ASystem and method for resetting a microprocessor systemS MOS SYSTEMS INC·Filed 1992·Granted Mar 22, 1994·11 cites·6 claims
Showing the top 50 of 51 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →