Inventor · disambiguated record
Yoshie Nakabayashi
Also filed as: NAKABAYASHI YOSHIE
10 granted patents·1 pending application·20 citations·filing 2016–2024
85Inventor score
Files withRAMBUS INC11
Top patents by PatentIndex Score
11 records- 0196US11294830B2Training and operations with a double buffered memory topologyRAMBUS INC·Filed 2020·Granted Apr 5, 2022·8 cites·18 claims
- 0288US10613995B2Training and operations with a double buffered memory topologyRAMBUS INC·Filed 2016·Granted Apr 7, 2020·7 cites·18 claims
- 0387US11768780B2Training and operations with a double buffered memory topologyRAMBUS INC·Filed 2022·Granted Sep 26, 2023·1 cites·20 claims
- 0484US10169258B2Memory system design using buffer(s) on a mother boardRAMBUS INC·Filed 2016·Granted Jan 1, 2019·3 cites·17 claims
- 0581US2025110897A1Training and operations with a double buffered memory topologyRAMBUS INC·Filed 2024·Application pending·0 cites
- 0678US12141081B2Training and operations with a double buffered memory topologyRAMBUS INC·Filed 2023·Granted Nov 12, 2024·0 cites·20 claims
- 0777US11907139B2Memory system design using buffer(s) on a mother boardRAMBUS INC·Filed 2022·Granted Feb 20, 2024·0 cites·18 claims
- 0871US11537540B2Memory system design using buffer(s) on a mother boardRAMBUS INC·Filed 2021·Granted Dec 27, 2022·0 cites·20 claims
- 0968US11003601B2Memory system design using buffer(s) on a mother boardRAMBUS INC·Filed 2020·Granted May 11, 2021·0 cites·20 claims
- 1065US10255220B2Dynamic termination scheme for memory communicationRAMBUS INC·Filed 2016·Granted Apr 9, 2019·1 cites·18 claims
- 1164US10614002B2Memory system design using buffer(S) on a mother boardRAMBUS INC·Filed 2018·Granted Apr 7, 2020·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →