Inventor · disambiguated record
Yuan-Hung Chiu
Also filed as: CHIU YUAN-HUNG
40 granted patents·8 pending applications·786 citations·filing 1999–2022
98Inventor score
Top patents by PatentIndex Score
48 records- 0197US8236659B2Source and drain feature profile for improving device performance and method of manufacturing sameTSAI MING-HUAN·Filed 2010·Granted Aug 7, 2012·41 cites·7 claims
- 0295US11437498B2FinFET device and methodTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Sep 6, 2022·4 cites·20 claims
- 0395US6869868B2Method of fabricating a MOSFET device with metal containing gate structuresTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Mar 22, 2005·134 cites·32 claims
- 0494US9627258B1Method of forming a contactTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Apr 18, 2017·9 cites·20 claims
- 0594US6407002B1Partial resist free approach in contact etch to improve W-fillingTAIWAN SEMICONDUCTOR MFG·Filed 2000·Granted Jun 18, 2002·83 cites·27 claims
- 0692US8614132B2Integrated circuit device with well controlled surface proximity and method of manufacturing sameTSAI MING-HUAN·Filed 2011·Granted Dec 24, 2013·10 cites·19 claims
- 0790US10861960B1FinFET device and methodTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Dec 8, 2020·5 cites·20 claims
- 0889US8900960B2Integrated circuit device with well controlled surface proximity and method of manufacturing sameTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Dec 2, 2014·6 cites·21 claims
- 0989US7078351B2Photoresist intensive patterning and processingTAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted Jul 18, 2006·44 cites·7 claims
- 1088US7301645B2In-situ critical dimension measurementTAIWAN SEMICONDUCTOR MFG·Filed 2005·Granted Nov 27, 2007·14 cites·20 claims
- 1188US7012027B2Zirconium oxide and hafnium oxide etching using halogen containing chemicalsTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Mar 14, 2006·44 cites·14 claims
- 1287US6867084B1Gate structure and method of forming the gate dielectric with mini-spacerTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Mar 15, 2005·31 cites·22 claims
- 1386US10164032B2Self-aligned contact and manufacturing method thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Dec 25, 2018·4 cites·20 claims
- 1485US7109085B2Etching process to avoid polysilicon notchingTAIWAN SEMICONDUCTOR MFG·Filed 2005·Granted Sep 19, 2006·10 cites·27 claims
- 1585US6818553B1Etching process for high-k gate dielectricsTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Nov 16, 2004·27 cites·37 claims
- 1684US6764903B1Dual hard mask layer patterning methodTAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted Jul 20, 2004·32 cites·20 claims
- 1782US7390753B2In-situ plasma treatment of advanced resists in fine pattern definitionTAIWAN SEMICONDUCTOR MFG·Filed 2005·Granted Jun 24, 2008·9 cites·20 claims
- 1882US7074727B2Process for improving dielectric properties in low-k organosilicate dielectric materialTAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted Jul 11, 2006·17 cites·14 claims
- 1980US10032887B2Method of forming a contactTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Jul 24, 2018·2 cites·20 claims
- 2079US6884736B2Method of forming contact plug on silicide structureTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Apr 26, 2005·20 cites·43 claims
- 2179US6297162B1Method to reduce silicon oxynitride etch rate in a silicon oxide dry etchTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Oct 2, 2001·67 cites·6 claims
- 2277US7195969B2Strained channel CMOS device with fully silicided gate electrodeTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Mar 27, 2007·23 cites·21 claims
- 2377US7008878B2Plasma treatment and etching process for ultra-thin dielectric filmsTAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted Mar 7, 2006·18 cites·17 claims
- 2477US6333271B1Multi-step plasma etch method for plasma etch processing a microelectronic layerTAIWAN SEMICONDUCTOR MFG·Filed 2001·Granted Dec 25, 2001·14 cites·16 claims
- 2576US11735651B2FinFET device and methodTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Aug 22, 2023·0 cites·20 claims
- 2676US6524938B1Method for gate formation with improved spacer profile controlTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Feb 25, 2003·19 cites·42 claims
- 2773US6849531B1Phosphoric acid free process for polysilicon gate definitionTAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted Feb 1, 2005·15 cites·27 claims
- 2873US6777340B1Method of etching a silicon containing layer using multilayer masksTAIWAN SEMICONDUCTOR MFG·Filed 2001·Granted Aug 17, 2004·17 cites·26 claims
- 2973US6503848B1Method of forming a smooth polysilicon surface using a soft etch to enlarge the photo lithography windowTAIWAN SEMICONDUCTOR MFG·Filed 2001·Granted Jan 7, 2003·15 cites·21 claims
- 3062US6828237B1Sidewall polymer deposition method for forming a patterned microelectronic layerTAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted Dec 7, 2004·8 cites·20 claims
- 3161US6812044B2Advanced control for plasma processTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Nov 2, 2004·7 cites·11 claims
- 3259US9349831B2Integrated circuit device with well controlled surface proximity and method of manufacturing sameTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted May 24, 2016·0 cites·20 claims
- 3359US6900104B1Method of forming offset spacer manufacturing for critical dimension precisionTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted May 31, 2005·6 cites·21 claims
- 3458US6235653B1Ar-based si-rich oxynitride film for dual damascene and/or contact etch stop layerTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted May 22, 2001·24 cites·20 claims
- 3556US7678655B2Spacer layer etch method providing enhanced microelectronic device performanceTAIWAN SEMICONDUCTOR MFG·Filed 2006·Granted Mar 16, 2010·1 cites·20 claims
- 3654US10825907B2Self-aligned contact and manufacturing method thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Nov 3, 2020·0 cites·20 claims
- 3753US6828198B2System-on-chip (SOC) solutions with multiple devices by multiple poly gate trimming processTAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted Dec 7, 2004·4 cites·43 claims
- 3848US2005127459A1Novel gate structure and method of forming the gate dielectric with mini-spacerTAIWAN SEMICONDUCTOR MFG·Filed 2005·Application pending·0 cites
- 3945US7060628B2Method for fabricating a hard mask polysilicon gateTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Jun 13, 2006·2 cites·13 claims
- 4044US7510940B2Method for fabricating dual-gate semiconductor deviceTAIWAN SEMICONDUCTOR MFG·Filed 2007·Granted Mar 31, 2009·0 cites·14 claims
- 4144US2005042859A1Etching process for high-k gate dielectricsTAIWAN SEMICONDUCTOR MFG·Filed 2004·Application pending·0 cites
- 4243US7307009B2Phosphoric acid free process for polysilicon gate definitionTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Dec 11, 2007·0 cites·13 claims
- 4339US2005106888A1Method of in-situ damage removal - post O2 dry processTAIWAN SEMICONDUCTOR MFG·Filed 2003·Application pending·0 cites
- 4438US2005081781A1Fully dry, Si recess free process for removing high k dielectric layerTAIWAN SEMICONDUCTOR MFG·Filed 2003·Application pending·0 cites
- 4537US2011039390A1Reducing Local Mismatch of Devices Using Cryo-ImplantationTAIWAN SEMICONDUCTOR MFG·Filed 2010·Application pending·0 cites
- 4637US2011256682A1Multiple Deposition, Multiple Treatment Dielectric Layer For A Semiconductor DeviceTAIWAN SEMICONDUCTOR MFG·Filed 2010·Application pending·0 cites
- 4737US2004214448A1Method of ashing a photoresistTAIWAN SEMICONDUCTOR MFG·Filed 2003·Application pending·0 cites
- 4836US2005092348A1Method for cleaning an integrated circuit device using an aqueous cleaning compositionFiled 2003·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →