Inventor · disambiguated record
Yuan-Te Hou
Also filed as: HOU YUAN-TE
77 granted patents·4 pending applications·491 citations·filing 2009–2025
99Inventor score
Files withTAIWAN SEMICONDUCTOR MFG CO LTD54TAIWAN SEMICONDUCTOR MFG10CHEN HUANG-YU6LU LEE-CHUNG5CHANG SHIH-MING2
Top patents by PatentIndex Score
81 records- 0197US11113443B1Integrated circuit with thicker metal lines on lower metallization layerTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Sep 7, 2021·6 cites·20 claims
- 0297US8826212B2Method of forming a layout including cells having different threshold voltages, a system of implementing and a layout formedTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Sep 2, 2014·112 cites·20 claims
- 0397US8584052B2Cell layout for multiple patterning technologyCHEN HUANG-YU·Filed 2011·Granted Nov 12, 2013·26 cites·19 claims
- 0497US8448100B1Tool and method for eliminating multi-patterning conflictsLIN HUNG LUNG·Filed 2012·Granted May 21, 2013·102 cites·18 claims
- 0594US11574108B2Block level design method for heterogeneous PG-structure cellsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Feb 7, 2023·2 cites·20 claims
- 0693US9543193B2Non-hierarchical metal layers for integrated circuitsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Jan 10, 2017·8 cites·20 claims
- 0793US8418111B2Method and apparatus for achieving multiple patterning technology compliant design layoutCHEN HUANG-YU·Filed 2010·Granted Apr 9, 2013·29 cites·28 claims
- 0893US8255837B2Methods for cell boundary isolation in double patterning designLU LEE-CHUNG·Filed 2009·Granted Aug 28, 2012·19 cites·20 claims
- 0991US10050028B2Semiconductor device with reduced leakage currentTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Aug 14, 2018·8 cites·20 claims
- 1091US9971863B2Rule checking for multiple patterning technologyTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted May 15, 2018·7 cites·20 claims
- 1191US8239806B2Routing system and method for double patterning technologyCHEN HUANG-YU·Filed 2009·Granted Aug 7, 2012·27 cites·19 claims
- 1290US12402384B2Standard cell design with dummy paddingTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Aug 26, 2025·1 cites·20 claims
- 1390US9558312B2Electromigration resistant standard cell deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Jan 31, 2017·7 cites·20 claims
- 1490US8959466B1Systems and methods for designing layouts for semiconductor device fabricationTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Feb 17, 2015·6 cites·20 claims
- 1589US10089433B2Method for triple-patterning friendly placementTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Oct 2, 2018·6 cites·20 claims
- 1689US9117882B2Non-hierarchical metal layers for integrated circuitsLU LEE-CHUNG·Filed 2011·Granted Aug 25, 2015·8 cites·20 claims
- 1789US8907497B2Semiconductor device with self-aligned interconnects and blocking portionsCHANG SHIH-MING·Filed 2012·Granted Dec 9, 2014·11 cites·18 claims
- 1887US8431968B2Electromigration resistant standard cell deviceLU LEE-CHUNG·Filed 2010·Granted Apr 30, 2013·8 cites·20 claims
- 1986US11593546B2Integrated circuit with thicker metal lines on lower metallization layerTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Feb 28, 2023·1 cites·20 claims
- 2086US11055466B2Block level design method for heterogeneous PG-structure cellsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Jul 6, 2021·2 cites·20 claims
- 2186US8631366B2Integrated circuit design using DFM-enhanced architectureHOU YUNG-CHIN·Filed 2010·Granted Jan 14, 2014·10 cites·33 claims
- 2285US9087170B2Cell layout design and methodTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2013·Granted Jul 21, 2015·8 cites·20 claims
- 2385US9035361B2Electromigration resistant standard cell deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2013·Granted May 19, 2015·6 cites·20 claims
- 2484US8977991B2Method and system for replacing a pattern in a layoutTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2013·Granted Mar 10, 2015·6 cites·20 claims
- 2583US12131109B2Block level design method for heterogeneous PG-structure cellsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Oct 29, 2024·0 cites·20 claims
- 2683US8914755B1Layout re-decomposition for multiple patterning layoutsTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Dec 16, 2014·7 cites·20 claims
- 2783US8601408B2Method and system for replacing a pattern in a layoutCHEN HUANG-YU·Filed 2011·Granted Dec 3, 2013·6 cites·19 claims
- 2882US9317650B2Double patterning technology (DPT) layout routingTAIWAN SEMICONDUCTOR MFG·Filed 2014·Granted Apr 19, 2016·5 cites·20 claims
- 2981US9768119B2Apparatus and method for mitigating dynamic IR voltage drop and electromigration affectsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2013·Granted Sep 19, 2017·6 cites·17 claims
- 3081US9064081B1Generating database for cells routable in pin layerTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Jun 23, 2015·6 cites·13 claims
- 3181US8211807B2Double patterning technology using single-patterning-spacer-techniqueCHEN HUANG-YU·Filed 2010·Granted Jul 3, 2012·5 cites·10 claims
- 3280US12229489B2System and method of verifying slanted layout componentsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Feb 18, 2025·0 cites·20 claims
- 3380US11853678B2Block level design method for heterogeneous PG-structure cellsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Dec 26, 2023·0 cites·20 claims
- 3479US11030381B2Leakage analysis on semiconductor deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Jun 8, 2021·2 cites·20 claims
- 3578US8117575B2System and method for on-chip-variation analysisLU LEE-CHUNG·Filed 2009·Granted Feb 14, 2012·8 cites·20 claims
- 3678US2025324702A1Standard cell design with dummy paddingTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 3777US9627310B2Semiconductor device with self-aligned interconnectsCHANG SHIH-MING·Filed 2012·Granted Apr 18, 2017·4 cites·18 claims
- 3876US12008302B2Integrated circuit with thicker metal lines on lower metallization layerTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Jun 11, 2024·0 cites·20 claims
- 3976US10671788B2Method, system, and storage medium of resource planning for designing semiconductor deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Jun 2, 2020·1 cites·20 claims
- 4075US8898600B2Layout optimization for integrated designTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Nov 25, 2014·3 cites·19 claims
- 4174US10565341B2Constrained cell placementTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Feb 18, 2020·1 cites·20 claims
- 4274US2025165694A1System and method of verifying slanted layout componentsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 4373US9935057B2Multiple driver pin integrated circuit structureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Apr 3, 2018·2 cites·20 claims
- 4471US11861288B2System and method of verifying slanted layout componentsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Jan 2, 2024·0 cites·7 claims
- 4571US9418196B2Layout optimization for integrated circuit designTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Aug 16, 2016·1 cites·20 claims
- 4670US11574106B2Method, system, and storage medium of resource planning for designing semiconductor deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Feb 7, 2023·0 cites·20 claims
- 4770US8875067B2Reusable cut mask for multiple layersTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Oct 28, 2014·2 cites·20 claims
- 4869US9659133B2Method, system and computer program product for generating layout for semiconductor deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2013·Granted May 23, 2017·2 cites·20 claims
- 4968US11714949B2Leakage analysis on semiconductor deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Aug 1, 2023·0 cites·20 claims
- 5068US10956643B2Method, system, and storage medium of resource planning for designing semiconductor deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Mar 23, 2021·0 cites·20 claims
Showing the top 50 of 81 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →