Inventor · disambiguated record
Yu-Tsang Hsieh
Also filed as: Hsieh Yu-Tsang
6 granted patents·3 pending applications·5 citations·filing 2016–2023
68Inventor score
Files withANAGLOBE TECH INC9
Top patents by PatentIndex Score
9 records- 0180US9830416B2Method for analog circuit placementANAGLOBE TECH INC·Filed 2016·Granted Nov 28, 2017·5 cites·12 claims
- 0259US12475291B2Method for generating analog schematic diagram based on building block classification and reinforcement learningANAGLOBE TECH INC·Filed 2022·Granted Nov 18, 2025·0 cites·20 claims
- 0355US12190033B2Method for parallelism-aware wavelength-routed optical networks-on-chip designANAGLOBE TECH INC·Filed 2022·Granted Jan 7, 2025·0 cites·20 claims
- 0453US11177901B1Method of wavelength-division-multiplexing-aware clustering for on-chip optical routingANAGLOBE TECH INC·Filed 2020·Granted Nov 16, 2021·0 cites·20 claims
- 0550US12346646B2Method of warpage-aware floorplanning for heterogeneous integration structureANAGLOBE TECH INC·Filed 2022·Granted Jul 1, 2025·0 cites·20 claims
- 0647US2024284078A1Method for generating a customized WRONoC topologyANAGLOBE TECH INC·Filed 2023·Application pending·0 cites
- 0745US2022215146A1Method for recognizing analog circuit structureANAGLOBE TECH INC·Filed 2022·Application pending·0 cites
- 0841US10635771B2Method for parasitic-aware capacitor sizing and layout generationANAGLOBE TECH INC·Filed 2017·Granted Apr 28, 2020·0 cites·20 claims
- 0940US2022058325A1Method for Recognizing Analog Circuit StructureANAGLOBE TECH INC·Filed 2020·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →