Inventor · disambiguated record
Yu-Hsiang Kao
Also filed as: KAO YU-HSIANG
7 granted patents·2 pending applications·4 citations·filing 2012–2025
73Inventor score
Top patents by PatentIndex Score
9 records- 0185US2025362581A1Euv lithography mask blanks, euv masks and methodsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 0277US2025216764A1Euv lithography mask blanks, euv masks and methodsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 0375US8898600B2Layout optimization for integrated designTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Nov 25, 2014·3 cites·19 claims
- 0471US9418196B2Layout optimization for integrated circuit designTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Aug 16, 2016·1 cites·20 claims
- 0568US11865518B2Method for manufacturing electroless plating substrate and method for forming metal layer on surface of substrateUNIV NAT TSING HUA·Filed 2020·Granted Jan 9, 2024·0 cites·20 claims
- 0665US10828624B2Self-adsorbed catalyst composition, method for preparing the same and method for manufacturing electroless plating substrateUNIV NAT TSING HUA·Filed 2018·Granted Nov 10, 2020·0 cites·5 claims
- 0757US9292645B2Layout optimization for integrated circuit designTAIWAN SEMICONDUCTOR MFG·Filed 2014·Granted Mar 22, 2016·0 cites·20 claims
- 0854US9754073B2Layout optimization for integrated circuit designTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Sep 5, 2017·0 cites·20 claims
- 0941US9553043B2Interconnect structure having smaller transition layer viaLU LEE-CHUNG·Filed 2012·Granted Jan 24, 2017·0 cites·10 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →