Inventor · disambiguated record
Yung-Liang Kuo
Also filed as: KUO YUNG-LIANG
11 granted patents·81 citations·filing 2006–2024
87Inventor score
Top patents by PatentIndex Score
11 records- 0193US7598523B2Test structures for stacking dies having through-silicon viasTAIWAN SEMICONDUCTOR MFG·Filed 2007·Granted Oct 6, 2009·52 cites·19 claims
- 0287US12313675B2Method and device for wafer-level testingTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Granted May 27, 2025·0 cites·20 claims
- 0387US12270852B2Method and system for wafer-level testingTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Granted Apr 8, 2025·0 cites·20 claims
- 0483US12066484B2Method and device for wafer-level testingTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Aug 20, 2024·0 cites·20 claims
- 0583US11073551B2Method and system for wafer-level testingTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Jul 27, 2021·1 cites·20 claims
- 0683US8248091B2Universal array type probe card design for semiconductor device testingCHENG HSU MING·Filed 2006·Granted Aug 21, 2012·18 cites·20 claims
- 0782US12025655B2Method and system for wafer-level testingTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Jul 2, 2024·0 cites·20 claims
- 0881US7781235B2Chip-probing and bumping solutions for stacked dies having through-silicon viasTAIWAN SEMICONDUCTOR MFG·Filed 2006·Granted Aug 24, 2010·10 cites·20 claims
- 0978US11754621B2Method and device for wafer-level testingTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Sep 12, 2023·0 cites·19 claims
- 1074US11630149B2Method and system for wafer-level testingTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Apr 18, 2023·0 cites·20 claims
- 1174US11448692B2Method and device for wafer-level testingTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Sep 20, 2022·0 cites·18 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →