Inventor · disambiguated record
Yu-Lan Lo
Also filed as: LO YU L · LO YU-LAN
20 granted patents·10 pending applications·6 citations·filing 2004–2025
88Inventor score
Top patents by PatentIndex Score
30 records- 0179US12260161B2Method for establishing variation model related to circuit characteristics for performing circuit simulation, and associated circuit simulation systemREALTEK SEMICONDUCTOR CORP·Filed 2022·Granted Mar 25, 2025·1 cites·10 claims
- 0265US9003341B2Method for determining interface timing of integrated circuit automatically and related machine readable medium thereofREALTEK SEMICONDUCTOR CORP·Filed 2013·Granted Apr 7, 2015·2 cites·19 claims
- 0363US9858382B2Computer program product for timing analysis of integrated circuitREALTEK SEMICONDUCTOR CORP·Filed 2015·Granted Jan 2, 2018·1 cites·6 claims
- 0461US12481815B2Circuit simulation method and circuit simulation systemREALTEK SEMICONDUCTOR CORP·Filed 2022·Granted Nov 25, 2025·0 cites·16 claims
- 0560US10657303B2Circuit encoding method and circuit structure recognition methodREALTEK SEMICONDUCTOR CORP·Filed 2018·Granted May 19, 2020·1 cites·11 claims
- 0660US8726206B1Deadlock detection method and related machine readable mediumREALTEK SEMICONDUCTOR CORP·Filed 2013·Granted May 13, 2014·1 cites·14 claims
- 0760US2025362706A1Electronic device and clock jitter analysis methodREALTEK SEMICONDUCTOR CORP·Filed 2025·Application pending·0 cites
- 0856US2025013814A1Estimation method used in integrated circuit chip of integrated circuit design and integrated circuit chipREALTEK SEMICONDUCTOR CORP·Filed 2024·Application pending·0 cites
- 0956US2024370616A1Critical path analysis method and electric deviceREALTEK SEMICONDUCTOR CORP·Filed 2024·Application pending·0 cites
- 1055US12488168B2Circuit verification methodREALTEK SEMICONDUCTOR CORP·Filed 2022·Granted Dec 2, 2025·0 cites·20 claims
- 1153US11194945B1Clock deadlock detecting system, method, and non-transitory computer readable storage mediumREALTEK SEMICONDUCTOR CORP·Filed 2021·Granted Dec 7, 2021·0 cites·20 claims
- 1253US10878151B1Glitch occurring point detection apparatus and methodREALTEK SEMICONDUCTOR CORP·Filed 2020·Granted Dec 29, 2020·0 cites·10 claims
- 1352US11455449B2Method for determining IC voltage and method for finding relation between voltages and circuit parametersREALTEK SEMICONDUCTOR CORP·Filed 2019·Granted Sep 27, 2022·0 cites·12 claims
- 1452US10909290B2Method of detecting a circuit malfunction and related deviceREALTEK SEMICONDUCTOR CORP·Filed 2020·Granted Feb 2, 2021·0 cites·8 claims
- 1551US11010521B2Method of detecting relations between pins of circuit and computer program product thereofREALTEK SEMICONDUCTOR CORP·Filed 2020·Granted May 18, 2021·0 cites·18 claims
- 1650US12039240B2Integrated circuit simulation and design method and system thereofREALTEK SEMICONDUCTOR CORP·Filed 2021·Granted Jul 16, 2024·0 cites·20 claims
- 1750US11314912B2IC design data base generating method, IC design method, and electronic device using the methodsREALTEK SEMICONDUCTOR CORP·Filed 2020·Granted Apr 26, 2022·0 cites·16 claims
- 1850US2023222277A1Margin calibration method and margin calibration system for static timing analysisREALTEK SEMICONDUCTOR CORP·Filed 2023·Application pending·0 cites
- 1948US10783293B2Circuit design system, checking method, and non-transitory computer readable medium thereofREALTEK SEMICONDUCTOR CORP·Filed 2018·Granted Sep 22, 2020·0 cites·20 claims
- 2047US10521529B2Simulation method for mixed-signal circuit system and related electronic deviceREALTEK SEMICONDUCTOR CORP·Filed 2017·Granted Dec 31, 2019·0 cites·8 claims
- 2146US11959956B2Circuit check method and electronic apparatusREALTEK SEMICONDUCTOR CORP·Filed 2020·Granted Apr 16, 2024·0 cites·8 claims
- 2245US2015067623A1Timing analysis method for non-standard cell circuit and associated machine readable mediumREALTEK SEMICONDUCTOR CORP·Filed 2014·Application pending·0 cites
- 2345US2005101304A1Mobile phone with auto-response capabilityFiled 2004·Application pending·0 cites
- 2444US2019384868A1Method and apparatus for adaptive voltage scaling to eliminate delay variation of whole designREALTEK SEMICONDUCTOR CORP·Filed 2019·Application pending·0 cites
- 2543US8713497B2Method of generating integrated circuit modelREALTEK SEMICONDUCTOR CORP·Filed 2013·Granted Apr 29, 2014·0 cites·9 claims
- 2642US2013298095A1Method for checking i/o cell connections and associated computer readable mediumREALTEK SEMICONDUCTOR CORP·Filed 2013·Application pending·0 cites
- 2739US2020285791A1Circuit design method and associated computer program productREALTEK SEMICONDUCTOR CORP·Filed 2020·Application pending·0 cites
- 2836US2006216614A1Method of mask making and structure thereof for improving mask ESD immunityTAIWAN SEMICONDUCTOR MFG·Filed 2005·Application pending·0 cites
- 2935US8443320B2Extracting methods for circuit modelsLEE MENG-JUNG·Filed 2011·Granted May 14, 2013·0 cites·14 claims
- 3034US8166433B2Method to inspect floating connection and floating net of integrated circuitLO YU-LAN·Filed 2009·Granted Apr 24, 2012·0 cites·14 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →