Inventor · disambiguated record
Yutaka Takikawa
Also filed as: TAKIKAWA YUTAKA
8 granted patents·2 pending applications·61 citations·filing 1997–2012
84Inventor score
Files withRENESAS TECH CORP6IWATA SHUNICHI1MITSUBISHI ELEC SEMICONDUCTOR1MITSUBISHI ELECTRIC CORP1SHIMIZU NOBUO1
Top patents by PatentIndex Score
10 records- 0177US7307889B2Semiconductor memoryRENESAS TECH CORP·Filed 2005·Granted Dec 11, 2007·6 cites·6 claims
- 0270US5912575APhase-locked loop circuit with charge pump and time constant circuitMITSUBISHI ELEC SEMICONDUCTOR·Filed 1997·Granted Jun 15, 1999·38 cites·4 claims
- 0368US8423850B2System debugging method, system debugging equipment, processor, wireless-communications interface IC and interface method thereofIWATA SHUNICHI·Filed 2007·Granted Apr 16, 2013·8 cites·34 claims
- 0458US7358548B2Semiconductor integrated circuit having layout in which buffers or protection circuits are arranged in concentrated mannerRENESAS TECH CORP·Filed 2006·Granted Apr 15, 2008·1 cites·8 claims
- 0551US6392497B1Phase-locked loop circuit with high lock speed and stabilityMITSUBISHI ELECTRIC CORP·Filed 2001·Granted May 21, 2002·8 cites·3 claims
- 0650US7742337B2Semiconductor memoryRENESAS TECH CORP·Filed 2008·Granted Jun 22, 2010·0 cites·2 claims
- 0748US7486556B2Semiconductor memoryRENESAS TECH CORP·Filed 2007·Granted Feb 3, 2009·0 cites·1 claims
- 0848US7400530B2Semiconductor memoryRENESAS TECH CORP·Filed 2007·Granted Jul 15, 2008·0 cites·3 claims
- 0948US2008149966A1Semiconductor integrated circuit having layout in which buffers or protection circuits are arranged in concentrated mannerRENESAS TECH CORP·Filed 2008·Application pending·0 cites
- 1038US2013314147A1Semiconductor processing device and semiconductor processing systemSHIMIZU NOBUO·Filed 2012·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →