Inventor · disambiguated record
Yvon Gris
Also filed as: GRIS YVON
34 granted patents·4 pending applications·334 citations·filing 1984–2006
97Inventor score
Files withST MICROELECTRONICS SA22SGS THOMSON MICROELECTRONICS11EFCIS2SGS THOMSON MICROELECTRONCIS S1
Top patents by PatentIndex Score
38 records- 0184US5953600AFabrication of bipolar/CMOS integrated circuitsSGS THOMSON MICROELECTRONICS·Filed 1997·Granted Sep 14, 1999·61 cites·6 claims
- 0275US6319786B1Self-aligned bipolar transistor manufacturing methodST MICROELECTRONICS SA·Filed 2000·Granted Nov 20, 2001·21 cites·6 claims
- 0375US6156594AFabrication of bipolar/CMOS integrated circuits and of a capacitorSGS THOMSON MICROELECTRONICS·Filed 1997·Granted Dec 5, 2000·37 cites·37 claims
- 0468US7470585B2Integrated circuit and fabrication processST MICROELECTRONICS SA·Filed 2006·Granted Dec 30, 2008·1 cites·20 claims
- 0567US4561932AMethod of producing integrated silicon structures on isolated islets of the substrateEFCIS·Filed 1984·Granted Dec 31, 1985·31 cites·3 claims
- 0666US6180442B1Bipolar transistor with an inhomogeneous emitter in a BICMOS integrated circuit methodSGS THOMSON MICROELECTRONICS·Filed 1997·Granted Jan 30, 2001·26 cites·38 claims
- 0763US6376883B1Bipolar transistor and capacitorSGS THOMSON MICROELECTRONICS·Filed 2000·Granted Apr 23, 2002·9 cites·15 claims
- 0862US6352907B1Method for manufacturing bipolar devices with a self-aligned base-emitter junctionST MICROELECTRONICS SA·Filed 2000·Granted Mar 5, 2002·10 cites·23 claims
- 0961US5970333ADielectric isolation bipolar transistorSGS THOMSON MICROELECTRONICS·Filed 1997·Granted Oct 19, 1999·24 cites·12 claims
- 1057US6806536B2Multiple-function electronic chipST MICROELECTRONICS SA·Filed 2001·Granted Oct 19, 2004·7 cites·26 claims
- 1156US7115933B2Integrated circuit and fabrication processST MICROELECTRONICS SA·Filed 2002·Granted Oct 3, 2006·5 cites·24 claims
- 1253US6432789B2Method of forming a well isolation bipolar transistorSGS THOMSON MICROELECTRONICS·Filed 2000·Granted Aug 13, 2002·4 cites·20 claims
- 1351US6689672B2Buried layer manufacturing methodST MICROELECTRONICS SA·Filed 2001·Granted Feb 10, 2004·5 cites·24 claims
- 1451US6537873B2Integrated circuit comprising a memory cell of the DRAM type, and fabrication processST MICROELECTRONICS SA·Filed 2002·Granted Mar 25, 2003·3 cites·14 claims
- 1551US6506655B1Bipolar transistor manufacturing methodST MICROELECTRONICS SA·Filed 2000·Granted Jan 14, 2003·6 cites·12 claims
- 1650US6670657B2Integrated circuit having photodiode device and associated fabrication processST MICROELECTRONICS SA·Filed 2002·Granted Dec 30, 2003·2 cites·14 claims
- 1750US6607960B2Bipolar transistor manufacturing methodST MICROELECTRONICS SA·Filed 2001·Granted Aug 19, 2003·4 cites·22 claims
- 1849US4891328AMethod of manufacturing field effect transistors and lateral bipolar transistors on the same substrateEFCIS·Filed 1986·Granted Jan 2, 1990·17 cites·7 claims
- 1948US7060596B2Process for fabricating a single-crystal substrate and integrated circuit comprising such a substrateST MICROELECTRONICS SA·Filed 2002·Granted Jun 13, 2006·2 cites·12 claims
- 2048US6614114B2Conductive line formed on integrated circuitsST MICROELECTRONICS SA·Filed 2001·Granted Sep 2, 2003·2 cites·39 claims
- 2148US6156616AMethod for fabricating an NPN transistor in a BICMOS technologySGS THOMSON MICROELECTRONICS·Filed 1997·Granted Dec 5, 2000·8 cites·10 claims
- 2245US6376322B1Base-emitter region of a submicronic bipolar transistorST MICROELECTRONICS SA·Filed 1999·Granted Apr 23, 2002·9 cites·29 claims
- 2345US6258720B1Method of formation of conductive lines on integrated circuitsST MICROELECTRONICS SA·Filed 1999·Granted Jul 10, 2001·10 cites·25 claims
- 2445US2006068558A1Process and installation for doping an etched pattern of resistive elementsST MICROELECTRONICS SA·Filed 2005·Application pending·0 cites
- 2543US6984872B2Method for fabricating an NPN transistor in a BICMOS technologySGS THOMSON MICROELECTRONICS·Filed 2004·Granted Jan 10, 2006·1 cites·20 claims
- 2643US6607961B1Method of definition of two self-aligned areas at the upper surface of a substrateST MICROELECTRONICS SA·Filed 2000·Granted Aug 19, 2003·1 cites·6 claims
- 2743US5880000AMethod for fabricating an NPN transistor of minimum surfaceSGS THOMSON MICROELECTRONICS·Filed 1997·Granted Mar 9, 1999·8 cites·18 claims
- 2842US7112461B2Fabrication process for integrated circuit having photodiode deviceST MICROELECTRONICS SA·Filed 2003·Granted Sep 26, 2006·0 cites·8 claims
- 2940US6989310B2Process and installation for doping an etched pattern of resistive elementsST MICROELECTRONICS SA·Filed 2003·Granted Jan 24, 2006·0 cites·17 claims
- 3039US6184102B1Method for manufacturing a well isolation bipolar transistorSGS THOMSON MICROELECTRONICS·Filed 1997·Granted Feb 6, 2001·4 cites·18 claims
- 3139US2005017325A1Method for fabricating an NPN transistor in a BICMOS technologyFiled 2004·Application pending·0 cites
- 3238US6864542B2Bipolar transistor manufacturing methodST MICROELECTRONICS SA·Filed 2003·Granted Mar 8, 2005·0 cites·22 claims
- 3338US2003102577A1Method of definition of two self-aligned areas at the upper surface of a substrateST MICROELECTRONICS SA·Filed 2002·Application pending·0 cites
- 3435US6114743AWell isolation bipolar transistorSGS THOMSON MICROELECTRONICS·Filed 1999·Granted Sep 5, 2000·2 cites·11 claims
- 3535US2002053316A1Method of deposition of a single-crystal silicon regionFiled 2001·Application pending·0 cites
- 3634US6165265AMethod of deposition of a single-crystal silicon regionST MICROELECTRONICS SA·Filed 1999·Granted Dec 26, 2000·5 cites·10 claims
- 3732US6187646B1Method of manufacturing a capacitor as part of an integrated semiconductor circuitSGS THOMSON MICROELECTRONCIS S·Filed 1997·Granted Feb 13, 2001·4 cites·21 claims
- 3827US6372570B1Method of formation of a capacitor on an integrated circuitST MICROELECTRONICS SA·Filed 1999·Granted Apr 16, 2002·5 cites·16 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →