Inventor · disambiguated record
Zainab Nasreen Zaidi
Also filed as: ZAIDI ZAINAB NASREEN · ZAIDI Zainab
10 granted patents·4 pending applications·43 citations·filing 2016–2024
87Inventor score
Top patents by PatentIndex Score
14 records- 0197US11049586B2Systems and methods for implementing redundancy for tile-based intelligence processing computing architectureMYTHIC INC·Filed 2020·Granted Jun 29, 2021·8 cites·16 claims
- 0296US11016810B1Tile subsystem and method for automated data flow and data processing within an integrated circuit architectureMYTHIC INC·Filed 2020·Granted May 25, 2021·15 cites·15 claims
- 0394US11360932B2Systems and methods for implementing an intelligence processing computing architectureMYTHIC INC·Filed 2020·Granted Jun 14, 2022·5 cites·18 claims
- 0491US10521395B1Systems and methods for implementing an intelligence processing computing architectureMYTHIC INC·Filed 2019·Granted Dec 31, 2019·6 cites·16 claims
- 0588US12013807B2Systems and methods for implementing an intelligence processing computing architectureMYTHIC INC·Filed 2022·Granted Jun 18, 2024·1 cites·18 claims
- 0686US10606797B2Systems and methods for implementing an intelligence processing computing architectureMYTHIC INC·Filed 2019·Granted Mar 31, 2020·3 cites·12 claims
- 0782US10114729B2Performance analysis using performance counters and trace logicQUALCOMM INC·Filed 2016·Granted Oct 30, 2018·5 cites·23 claims
- 0881US12461888B2Systems and methods for implementing an intelligence processing computing architectureMYTHIC INC·Filed 2024·Granted Nov 4, 2025·0 cites·16 claims
- 0978US2024311194A1Tile subsystem and method for automated data flow and data processing within an integrated circuit architectureMYTHIC INC·Filed 2024·Application pending·0 cites
- 1069US12014214B2Tile subsystem and method for automated data flow and data processing within an integrated circuit architectureMYTHIC INC·Filed 2021·Granted Jun 18, 2024·0 cites·19 claims
- 1166US11475973B2Systems and methods for implementing redundancy for tile-based intelligence processing computing architectureMYTHIC INC·Filed 2021·Granted Oct 18, 2022·0 cites·20 claims
- 1233US2019089619A1Self-test engine for network on chipQUALCOMM INC·Filed 2017·Application pending·0 cites
- 1332US2019094939A1Method and apparatus for preemptively scaling transactions to minimize power virus effectsQUALCOMM INC·Filed 2017·Application pending·0 cites
- 1431US2019020586A1Selective insertion of a deadlock recovery buffer in a bus interconnect for deadlock recoveryQUALCOMM INC·Filed 2017·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →