Inventor · disambiguated record
Zicheng Gary Ling
Also filed as: LING ZICHENG · LING ZICHENG G · LING ZICHENG GARY
24 granted patents·1 pending application·445 citations·filing 1998–2020
97Inventor score
Top patents by PatentIndex Score
25 records- 0187US6784685B2Testing vias and contacts in an integrated circuitXILINX INC·Filed 2002·Granted Aug 31, 2004·40 cites·7 claims
- 0287US6479350B1Reduced masking step CMOS transistor formation using removable amorphous silicon sidewall spacersADVANCED MICRO DEVICES INC·Filed 2000·Granted Nov 12, 2002·46 cites·18 claims
- 0385US6153455AMethod of fabricating ultra shallow junction CMOS transistors with nitride disposable spacerADVANCED MICRO DEVICES INC·Filed 1998·Granted Nov 28, 2000·63 cites·18 claims
- 0484US6287904B1Two step mask process to eliminate gate end cap shorteningADVANCED MICRO DEVICES INC·Filed 2000·Granted Sep 11, 2001·34 cites·9 claims
- 0583US6503765B1Testing vias and contacts in integrated circuit fabricationXILINX INC·Filed 2001·Granted Jan 7, 2003·29 cites·8 claims
- 0680US7109734B2Characterizing circuit performance by separating device and interconnect impact on signal delayXILINX INC·Filed 2003·Granted Sep 19, 2006·18 cites·8 claims
- 0778US7489152B2Characterizing circuit performance by separating device and interconnect impact on signal delayXILINX INC·Filed 2006·Granted Feb 10, 2009·7 cites·8 claims
- 0878US6551870B1Method of fabricating ultra shallow junction CMOS transistors with nitride disposable spacerADVANCED MICRO DEVICES INC·Filed 2000·Granted Apr 22, 2003·23 cites·3 claims
- 0976US7724016B2Characterizing circuit performance by separating device and interconnect impact on signal delayXILINX INC·Filed 2009·Granted May 25, 2010·6 cites·9 claims
- 1076US6868537B1Method of generating an IC mask using a reduced databaseXILINX INC·Filed 2002·Granted Mar 15, 2005·14 cites·9 claims
- 1170US10289784B1Determination of clock path delays and implementation of a circuit designXILINX INC·Filed 2017·Granted May 14, 2019·1 cites·16 claims
- 1269US6306702B1Dual spacer method of forming CMOS transistors with substantially the same sub 0.25 micron gate lengthADVANCED MICRO DEVICES INC·Filed 1999·Granted Oct 23, 2001·29 cites·14 claims
- 1367US6218224B1Nitride disposable spacer to reduce mask count in CMOS transistor formationADVANCED MICRO DEVICES INC·Filed 1999·Granted Apr 17, 2001·26 cites·19 claims
- 1467US6103563ANitride disposable spacer to reduce mask count in CMOS transistor formationADVANCED MICRO DEVICES INC·Filed 1999·Granted Aug 15, 2000·27 cites·17 claims
- 1565US6727710B1Structures and methods for determining the effects of high stress currents on conducting layers and contacts in integrated circuitsXILINX INC·Filed 2002·Granted Apr 27, 2004·8 cites·8 claims
- 1665US6482573B1Exposure correction based on reflective index for photolithographic process controlADVANCED MICRO DEVICES INC·Filed 2000·Granted Nov 19, 2002·8 cites·7 claims
- 1760US6368762B1Active mask exposure compensation of underlying nitride thickness variation to reduce critical dimension (CD) variationADVANCED MICRO DEVICES INC·Filed 2000·Granted Apr 9, 2002·7 cites·10 claims
- 1857US7046026B2Testing vias and contracts in integrated circuitXILINX INC·Filed 2004·Granted May 16, 2006·5 cites·13 claims
- 1956US6867580B1Structures and methods for determining the effects of high stress currents on conducting layers and contacts in integrated circuitsXILINX INC·Filed 2004·Granted Mar 15, 2005·5 cites·11 claims
- 2056US6166558AMethod for measuring gate length and drain/source gate overlapADVANCED MICRO DEVICES INC·Filed 1999·Granted Dec 26, 2000·20 cites·19 claims
- 2153US6265253B1Aluminum disposable spacer to reduce mask count in CMOS transistor formationADVANCED MICRO DEVICES INC·Filed 1999·Granted Jul 24, 2001·14 cites·17 claims
- 2252US2023129247A1High-boron cast steel material resisting high-temperature molten aluminum corrosion-abrasion and preparation method thereofUNIV SOUTH CHINA TECH·Filed 2020·Application pending·0 cites
- 2343US6842019B1Structures and methods for determining the effects of high stress currents on conducting layers and contacts in integrated circuitsXILINX INC·Filed 2004·Granted Jan 11, 2005·1 cites·12 claims
- 2443US6214655B1Amorphous silicon disposable spacer to reduce mask count in CMOS transistor formationADVANCED MICRO DEVICES INC·Filed 1999·Granted Apr 10, 2001·8 cites·17 claims
- 2540US6221706B1Aluminum disposable spacer to reduce mask count in CMOS transistor formationADVANCED MICRO DEVICES INC·Filed 1999·Granted Apr 24, 2001·6 cites·13 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →