Inventor · name-matched record
CHOI JIHONG
0 granted patents·13 pending applications·0 citations·filing 2024–2025
This identity is grouped by exact name match (no disambiguated inventor record was available for these filings) — it may combine same-named inventors.
Top patents by PatentIndex Score
13 records- 0170US2026066034A1Repair structure for extreme-bandwidth three-dimensional (3d) stacked dynamic random-access memory (dram) including base die for near-memory computingQUALCOMM INC·Filed 2025·Application pending·0 cites
- 0269US2026068182A1Through silicon via (tsv) bus compression-redistribution die for high-bandwidth three-dimensional dynamic random-access memory (3d dram) for flexible processing unit (pu) placement, improved thermal, and known good die (kgd) dram placement for high-yieldQUALCOMM INC·Filed 2025·Application pending·0 cites
- 0368US2026040923A1Three-dimensional stack with backside power distribution network (bspdn) contactsQUALCOMM INC·Filed 2025·Application pending·0 cites
- 0467US2026060041A1Dynamic random-access memory (dram) test pad arrangement method for a dram cell repair test on three-dimensional (3d) stacked dramQUALCOMM INC·Filed 2025·Application pending·0 cites
- 0567US2026068181A1Three-dimensional dynamic random-access memory (3d dram) structure with vertical separation of a memory cell arrayQUALCOMM INC·Filed 2025·Application pending·0 cites
- 0664US2026068623A1Memory device comprising multiple chips coupled together through fusion bondingQUALCOMM INC·Filed 2025·Application pending·0 cites
- 0764US2026068183A1High-capacity and high-bandwidth three-dimensional dynamic random-access memory (3d dram) integration in standard dram system-in-package (sip)QUALCOMM INC·Filed 2025·Application pending·0 cites
- 0864US2026068184A1Memory device comprising multiple chips with capacitor in processor in memory portionQUALCOMM INC·Filed 2025·Application pending·0 cites
- 0964US2026068767A1Flexible processing unit placement on stacked three-dimensional dynamic random-access memory (3d dram) for near-memory computingQUALCOMM INC·Filed 2025·Application pending·0 cites
- 1064US2026068624A1Memory device comprising multiple chips coupled together through hybrid bonding and fusion bondingQUALCOMM INC·Filed 2025·Application pending·0 cites
- 1164US2026060043A1Wafer and/or chip comprising memory cell structure and method for wafer quality assessmentQUALCOMM INC·Filed 2025·Application pending·0 cites
- 1262US2026057926A1Flexible refresh period control for dynamic random-access memory (dram) dies on a system-on-chip (soc) base die based on monitored temperature sensors of the dram diesQUALCOMM INC·Filed 2025·Application pending·0 cites
- 1360US2026101805A1Package comprising a stack of integrated devices and a plurality of wire bondsQUALCOMM INCORPORATED·Filed 2024·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when CHOI JIHONG files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: exact name match across USPTO filings. How scoring works →