Inventor · name-matched record
FROUGIER JULIEN
24 granted patents·6 pending applications·0 citations·filing 2021–2024
89Inventor score
This identity is grouped by exact name match (no disambiguated inventor record was available for these filings) — it may combine same-named inventors.
Top patents by PatentIndex Score
30 records- 0168US12557341B2Negative capacitance gate-all-around transistor with tunable capacitance ratioIBM·Filed 2023·Granted Feb 17, 2026·0 cites·20 claims
- 0268US12557356B2Semiconductor structure with fully wrapped-around backside contactIBM·Filed 2022·Granted Feb 17, 2026·0 cites·20 claims
- 0368US12557295B2Embedded ReRAM with backside contactIBM·Filed 2022·Granted Feb 17, 2026·0 cites·19 claims
- 0467US12575157B2Nanosheet with dual isolation regions separated by buried inner spacerIBM·Filed 2022·Granted Mar 10, 2026·0 cites·24 claims
- 0567US12550376B2Work function metal patterning and middle-of-line self-aligned contacts for nanosheet technologyIBM·Filed 2023·Granted Feb 10, 2026·0 cites·20 claims
- 0665US12588273B2Stacked electronic devices having independent gatesIBM·Filed 2023·Granted Mar 24, 2026·0 cites·20 claims
- 0765US12563972B2Magnetic tunnel junction pillar formation for MRAM deviceIBM·Filed 2021·Granted Feb 24, 2026·0 cites·10 claims
- 0865US12557354B2Vertical field-effect transistor (FET) stacked over horizontal FETIBM·Filed 2022·Granted Feb 17, 2026·0 cites·10 claims
- 0964US12563776B2Forming source/drain contact in a tight tip-to-tip spaceIBM·Filed 2023·Granted Feb 24, 2026·0 cites·20 claims
- 1064US12557338B2Semiconductor structure having a backside contact with backside sidewall spacersIBM·Filed 2022·Granted Feb 17, 2026·0 cites·20 claims
- 1163US12593457B2Multi-state ferroelectric-RAM with stacked capacitorsIBM·Filed 2022·Granted Mar 31, 2026·0 cites·16 claims
- 1263US12563747B2Three dimensional ReRAM deviceIBM·Filed 2022·Granted Feb 24, 2026·0 cites·9 claims
- 1363US2026090109A1Stacked fet with recessed channel transistors at bottomIBM·Filed 2024·Application pending·0 cites
- 1462US12550427B2Vertical inverter formation on stacked field effect transistor (SFET)IBM·Filed 2022·Granted Feb 10, 2026·0 cites·20 claims
- 1562US2026052751A1Forming shared source/drain contact with a gate-cut structureIBM·Filed 2024·Application pending·0 cites
- 1662US2026059843A1Removing high-k layer from inner spacerIBM·Filed 2024·Application pending·0 cites
- 1762US2026026070A1Source/drain contact in single diffusion break regionIBM·Filed 2024·Application pending·0 cites
- 1861US12593468B2Self-aligned backside contact with increased contact areaIBM·Filed 2022·Granted Mar 31, 2026·0 cites·20 claims
- 1961US12575140B2Diffusion break structure for transistorsIBM·Filed 2022·Granted Mar 10, 2026·0 cites·20 claims
- 2061US2026047191A1Fets with dummy nanosheetsIBM·Filed 2024·Application pending·0 cites
- 2160US12593501B2Stacked fork sheet devicesIBM·Filed 2022·Granted Mar 31, 2026·0 cites·20 claims
- 2260US2026075889A1Hybrid isolation pillarsIBM·Filed 2024·Application pending·0 cites
- 2359US12598776B2Nanosheet epitaxy with full bottom isolationINT BUSINESS MACHINES CORPORATION·Filed 2021·Granted Apr 7, 2026·0 cites·20 claims
- 2459US12568683B2Single stack dual channel gate-all-around nanosheet with strained PFET and bottom dielectric isolation NFETIBM·Filed 2022·Granted Mar 3, 2026·0 cites·17 claims
- 2558US12557353B2Method and structure for a logic device and another deviceIBM·Filed 2022·Granted Feb 17, 2026·0 cites·11 claims
- 2656US12575160B2Backside and frontside contacts for semiconductor deviceIBM·Filed 2022·Granted Mar 10, 2026·0 cites·20 claims
- 2755US12598759B2High-density metal-insulator-metal capacitor integration wth nanosheet stack technologyINT BUSINESS MACHINES CORPORATION·Filed 2021·Granted Apr 7, 2026·0 cites·19 claims
- 2854US12575145B2Monolithic stacked field effect transistor (SFET) with dual middle dielectric isolation (MDI) separationIBM·Filed 2022·Granted Mar 10, 2026·0 cites·10 claims
- 2954US12550338B2Three dimensional cross-point non-volatile memoryIBM·Filed 2022·Granted Feb 10, 2026·0 cites·10 claims
- 3053US12520564B2Optimizing stress in a hybrid vertical-PFET and horizontal-NFET nanosheet structureIBM·Filed 2021·Granted Jan 6, 2026·0 cites·10 claims
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Identity basis: exact name match across USPTO filings. How scoring works →