Inventor · name-matched record
Lu chao-chun
4 granted patents·10 pending applications·0 citations·filing 2022–2025
55Inventor score
Files withND HI TECH LAB INC6ETRON TECH INC4INVENT AND COLLABORATION LABORATORY INC2INVENT AND COLLABORATION LABORATORY PTE LTD2
This identity is grouped by exact name match (no disambiguated inventor record was available for these filings) — it may combine same-named inventors.
Top patents by PatentIndex Score
14 records- 0183US2026033394A1High bandwidth memory stack with side edge interconnection and 3d ic structure with the sameND HI TECH LAB INC·Filed 2025·Application pending·0 cites
- 0281US2026076267A13d integrated circuit packageND HI TECH LAB INC·Filed 2025·Application pending·0 cites
- 0377US12598765B2Transistor with low leakage currents and manufacturing method thereofETRON TECH INC·Filed 2024·Granted Apr 7, 2026·0 cites·6 claims
- 0473US12593688B2Manufacturing method of diamond composite waferND HI TECH LAB INC·Filed 2022·Granted Mar 31, 2026·0 cites·25 claims
- 0572US2026032930A13d ic structureETRON TECH INC·Filed 2025·Application pending·0 cites
- 0667US12575084B2Memory structure having a buried word lineINVENT AND COLLABORATION LABORATORY PTE LTD·Filed 2023·Granted Mar 10, 2026·0 cites·18 claims
- 0767US2026045295A1Logic semiconductor die with multiple level caches operated at different voltagesINVENT AND COLLABORATION LABORATORY INC·Filed 2025·Application pending·0 cites
- 0865US2026068186A1High-bandwidth memory stack with side edge interconnection and liquid cooling structureND HI TECH LAB INC·Filed 2025·Application pending·0 cites
- 0965US2026026392A13d ic structureETRON TECH INC·Filed 2025·Application pending·0 cites
- 1065US2026060072A1Semiconductor device package with sidewall-coupled thermal element and method of manufacturing the sameETRON TECH INC·Filed 2025·Application pending·0 cites
- 1164US2026090421A1Composite substrate, semiconductor device using the same and manufacturing method thereofND HI TECH LAB INC·Filed 2025·Application pending·0 cites
- 1262US2026060112A1Panel-level semiconductor package structure and method for manufacturing thereofND HI TECH LAB INC·Filed 2025·Application pending·0 cites
- 1359US2026006865A1Transistor structure with multiple vertical thin bodiesINVENT AND COLLABORATION LABORATORY INC·Filed 2025·Application pending·0 cites
- 1456US12586630B2Memory array circuitINVENT AND COLLABORATION LABORATORY PTE LTD·Filed 2023·Granted Mar 24, 2026·0 cites·15 claims
Join the waitlist — get patent alerts
Get an alert when Lu chao-chun files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: exact name match across USPTO filings. How scoring works →