US10002873B2ActiveUtilityA1

Method of manufacturing semiconductor device

71
Assignee: SAMSUNG ELECTRONICS CO LTDPriority: Jul 25, 2016Filed: Jun 7, 2017Granted: Jun 19, 2018
Est. expiryJul 25, 2036(~10.1 yrs left)· nominal 20-yr term from priority
H10P 50/283H10P 50/73H10P 14/40H01L 27/10844H01L 21/31116H01L 21/31111H01L 21/283H10D 1/042H10B 12/31H10B 12/315H10B 12/34H10P 70/234H10B 12/053H10B 12/0335H10B 12/01
71
PatentIndex Score
2
Cited by
15
References
20
Claims

Abstract

A method of manufacturing a semiconductor device includes stacking a molding layer and a preliminary support layer on a substrate, forming a support layer having a plurality of openings by removing at least a portion of the preliminary support layer, forming a sacrificial layer by filling the plurality of openings with a different material from a material of the molding layer and from a material of the preliminary support layer, forming a plurality of vertical holes through the support layer and through the molding layer, forming a lower electrode within the plurality of vertical holes, and removing the sacrificial layer and the molding layer.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A method of manufacturing a semiconductor device, the method comprising:
 stacking a molding layer and a preliminary support layer on a substrate; 
 forming a support layer having a plurality of openings by removing at least a portion of the preliminary support layer; 
 forming a sacrificial layer by filling the plurality of openings with a different material from a material of the molding layer and from a material of the preliminary support layer; 
 forming a plurality of vertical holes through the support layer and through the molding layer; 
 forming a lower electrode within the plurality of vertical holes; and 
 removing the sacrificial layer and the molding layer. 
 
     
     
       2. The method of manufacturing a semiconductor device as claimed in  claim 1 , wherein forming the plurality of vertical holes includes forming at least a portion of the plurality of vertical holes at a boundary between the sacrificial layer and the support layer. 
     
     
       3. The method of manufacturing a semiconductor device as claimed in  claim 1 , wherein the molding layer is formed of a material having a predetermined etch selectivity with respect to the material of the support layer. 
     
     
       4. The method of manufacturing a semiconductor device as claimed in  claim 1 , wherein the sacrificial layer is formed of a material having a predetermined etch selectivity with respect to the material of the support layer. 
     
     
       5. The method of manufacturing a semiconductor device as claimed in  claim 1 , wherein the support layer is formed of at least one of a silicon nitride and a silicon carbon nitride, the sacrificial layer is formed of a silicon oxynitride, and the molding layer is formed of a silicon oxide. 
     
     
       6. The method of manufacturing a semiconductor device as claimed in  claim 1 , wherein the plurality of vertical holes are formed using a dry etching process. 
     
     
       7. The method of manufacturing a semiconductor device as claimed in  claim 1 , wherein the sacrificial layer and the molding layer are removed using a strip process. 
     
     
       8. The method of manufacturing a semiconductor device as claimed in  claim 7 , wherein the molding layer is removed by performing the strip process through a region from which the sacrificial layer is removed. 
     
     
       9. The method of manufacturing a semiconductor device as claimed in  claim 1 , wherein the lower electrode is formed to have a cylindrical shape. 
     
     
       10. The method of manufacturing a semiconductor device as claimed in  claim 1 , wherein the sacrificial layer is formed to have a plurality of regularly disposed regions. 
     
     
       11. The method of manufacturing a semiconductor device as claimed in  claim 1 , wherein an area of the sacrificial layer is smaller than an area of the support layer. 
     
     
       12. The method of manufacturing a semiconductor device as claimed in  claim 1 , wherein a thickness of the sacrificial layer is a same as a thickness of the support layer. 
     
     
       13. The method of manufacturing a semiconductor device as claimed in  claim 1 , wherein the molding layer is formed to be thicker than the support layer. 
     
     
       14. A method of manufacturing a semiconductor device, the method comprising:
 alternately stacking a plurality of support layers and a plurality of molding layers on a substrate, each of the support layers including a plurality of openings and a plurality of sacrificial layers within the plurality of openings; 
 forming a plurality of vertical holes through the plurality of support layers and through the plurality of molding layers; 
 forming a lower electrode within the plurality of vertical holes; 
 removing the plurality of sacrificial layers included in the plurality of support layers and the plurality of molding layers; and 
 sequentially forming a dielectric layer and an upper electrode on the lower electrode layer. 
 
     
     
       15. The method of manufacturing a semiconductor device as claimed in  claim 14 , wherein the plurality of sacrificial layers included in different support layers of the plurality of support layers are formed to overlap each other. 
     
     
       16. A method of manufacturing a semiconductor device, the method comprising:
 stacking a molding layer and a preliminary support layer on a substrate; 
 forming a support layer having a plurality of openings by removing at least a portion of the preliminary support layer; 
 forming a sacrificial layer by filling the plurality of openings in the support layer with a different material from a material of the molding layer and from a material of the preliminary support layer, dry etching rate of the materials of the sacrificial layer and of the support layer being similar; 
 forming a plurality of vertical holes through the support layer and through the molding layer by dry etching the support layer and the molding layer; 
 forming a lower electrode within the plurality of vertical holes; and 
 removing the sacrificial layer and the molding layer. 
 
     
     
       17. The method of manufacturing a semiconductor device as claimed in  claim 16 , wherein forming the sacrificial layer in the support layer includes forming the sacrificial layer to completely fill the plurality of openings in the support layer, such that top surfaces of the sacrificial and support layers face a same direction and are level with each other, and bottom surfaces of the sacrificial and support layers face a same direction and are level with each other. 
     
     
       18. The method of manufacturing a semiconductor device as claimed in  claim 17 , wherein forming the plurality of vertical holes includes forming at least a portion of the plurality of vertical holes at a boundary between the sacrificial layer and the support layer, such that each vertical hole at the boundary between the sacrificial layer and the support layer penetrates both the sacrificial layer and the support layer. 
     
     
       19. The method of manufacturing a semiconductor device as claimed in  claim 16 , wherein forming the sacrificial layer includes using a material that has a same wet etching rate as that of the material of the molding layer. 
     
     
       20. The method of manufacturing a semiconductor device as claimed in  claim 19 , wherein dry etching the support layer and the molding layer to form the plurality of vertical holes is simultaneous, and a subsequent removal of the sacrificial layer and the molding layer via wet etching is simultaneous.

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