Repair control device and semiconductor device including the same

Abstract

A repair control device for memory cells divided into a plurality of banks may include a failed address storage circuit configured to sort and store a plurality of failed addresses each containing a failed bank address and a failed row address, according to the failed row address, and store the failed row address by matching the failed row address with total failed bank information representing one or more failed banks indicated by the failed row address. The repair control device also includes an address comparison circuit configured to compare an input address to a pair comprised of the failed row address and the total failed bank information, stored in the failed address storage circuit, and generate a hit signal based on the comparison result. The repair control device further includes an address generation circuit configured to generate an access target address based on the hit signal.

What is claimed is: 
     
       1. A repair control device for memory cells divided into a plurality of banks, comprising:
 a failed address storage circuit configured to sort and store a plurality of failed addresses each containing a failed bank address and a failed row address, according to the failed row address, and store the failed row address by matching the failed row address with total failed bank information representing one or more failed banks indicated by the failed row address; 
 an address comparison circuit configured to compare an input address to a pair comprised of the failed row address and the total failed bank information, stored in the failed address storage circuit, and generate a hit signal based on the comparison result; and 
 an address generation circuit configured to generate an access target address based on the hit signal. 
 
     
     
       2. The repair control device of  claim 1 , wherein the failed address storage circuit comprises:
 a failed address converter configured to convert the failed bank address into a failed bank indication signal indicated by the failed address, and set the total failed bank information based on the failed bank indication signal; and 
 a fuse set latch array configured to store the pair of the total failed bank information and the failed row address. 
 
     
     
       3. The repair control device of  claim 2 , wherein the fuse set latch array comprises a total failed bank information region for storing the total failed bank information and a failed row address region for storing the failed row address. 
     
     
       4. The repair control device of  claim 3 , wherein the total failed bank information region has bits corresponding to the plurality of banks, respectively. 
     
     
       5. The repair control device of  claim 4 , wherein the failed address converter enables a bit of the total failed bank information region, the bit corresponding to the failed bank indication signal. 
     
     
       6. The repair control device of  claim 5 , wherein the failed address converter enables the bit of the total failed bank information region, corresponding to the failed bank indication signal, based on a result obtained by decoding the failed bank address. 
     
     
       7. The repair control device of  claim 1 , wherein the input address comprises an input bank address and an input row address, and
 the address comparison circuit comprises an input address converter configured to convert the input bank address into an input bank indication signal indicated by the input address. 
 
     
     
       8. The repair control device of  claim 7 , wherein the input address converter generates the input bank indication signal based on a result obtained by decoding the input bank address. 
     
     
       9. The repair control device of  claim 8 , wherein the address comparison circuit enables the hit signal, when the input bank indication signal corresponds to the total failed bank information and the input row address corresponds with the failed row address stored in the failed address storage circuit. 
     
     
       10. The repair control device of  claim 1 , wherein the address generation circuit comprises:
 an address converter configured to generate a repair address and a repair enable signal based on the hit signal; and 
 an address selector configured to select the input address or the repair address as the access target address based on the repair enable signal. 
 
     
     
       11. The repair control device of  claim 10 , wherein the address converter enables the repair enable signal when the hit signal is enabled. 
     
     
       12. The repair control device of  claim 11 , wherein the address selector selects the repair address as the access target address when the repair enable signal is enabled. 
     
     
       13. The repair control device of  claim 11 , wherein the address selector selects the input address as the access target address when the repair enable signal is disabled. 
     
     
       14. A semiconductor device comprising:
 a nonvolatile memory configured to store a plurality of failed addresses each containing a failed bank address and a failed row address; and 
 a repair control device configured to sort and store a failed address outputted from the nonvolatile memory according to the failed row address, wherein the repair control device matches the failed row address with total failed bank information representing one or more failed banks indicated by the failed row address, and stores the failed row address. 
 
     
     
       15. The semiconductor device of  claim 14 , wherein the repair control device comprises:
 a failed address storage circuit configured to store the failed row address matched with the total failed bank information; 
 an address comparison circuit configured to compare an input address to the pair of the failed row address and the total failed bank information, stored in the failed address storage circuit, and generate a hit signal based on the comparison result; and 
 an address generation circuit configured to generate an access target address based on the hit signal. 
 
     
     
       16. The semiconductor device of  claim 15 , wherein the failed address storage circuit comprises:
 a failed address converter configured to convert the failed bank address into a failed bank indication signal indicated by the failed address, and set the total failed bank information based on the failed bank indication signal; and 
 a fuse set latch array configured to store the pair of the total failed bank information and the failed row address. 
 
     
     
       17. The semiconductor device of  claim 16 , wherein the fuse set latch array comprises a total failed bank information region for storing the total failed bank information and a failed row address region for storing the failed row address. 
     
     
       18. The semiconductor device of  claim 17 , wherein the total failed bank information region has bits corresponding to the respective banks. 
     
     
       19. The semiconductor device of  claim 18 , wherein the failed address converter enables a bit of the total failed bank information region, the bit corresponding to the failed bank indication signal. 
     
     
       20. The semiconductor device of  claim 19 , wherein the failed address converter enables the bit of the total failed bank information region, corresponding to the failed bank indication signal, based on a result obtained by decoding the failed bank address.