Impedance measuring circuit

Abstract

An impedance measuring circuit has an amplification circuit connected to a target and to amplify a predetermined input signal with a gain corresponding to an impedance in the target and to output an output signal, a peak hold circuit to hold a peak value of the output signal and to output a hold value, and an impedance calculation circuit to calculate the impedance in the target based on the hold value.

The invention claimed is: 
     
       1. An impedance measuring circuit comprising:
 an amplification circuit connected to a target and to amplify a predetermined input signal with a gain corresponding to an impedance in the target and to output an output signal; 
 a peak hold circuit to hold a peak value of the output signal and to output a hold value; and 
 an impedance calculation circuit to calculate the impedance in the target based on the hold value, 
 wherein the amplification circuit comprises: 
 a resistor comprising one end supplied with the input signal; and 
 a differential amplifier comprising a first input node connected to another end of the resistor, a second input node supplied with a reference voltage, and an output node to amplify a difference between a voltage in the first input node and the reference voltage and to output the output signal, and 
 the target is connected between the first input node and the output node of the differential amplifier. 
 
     
     
       2. The impedance measuring circuit according to  claim 1 ,
 wherein the input signal is an AC signal, 
 the impedance calculation circuit comprises: 
 an AD converter to convert the hold value into a digital signal; and 
 a signal processing unit to calculate the impedance based on the digital signal, 
 a frequency of the AC signal being higher than a frequency that the AD converter can perform AD conversion with. 
 
     
     
       3. The impedance measuring circuit according to  claim 1 ,
 wherein the peak value comprises a maximum value and a minimum value of the output signal, 
 the hold value comprises a maximum hold value and a minimum hold value, and 
 the impedance calculation circuit calculates the impedance based on a difference between the maximum hold value and the minimum hold value. 
 
     
     
       4. The impedance measuring circuit according to  claim 1 ,
 wherein the peak hold circuit conducts sample-hold of the held peak value and outputs a sample-hold value as the hold value. 
 
     
     
       5. An impedance measuring circuit comprising:
 an amplification circuit connected to a target and to amplify a predetermined input signal with a gain corresponding to an impedance in the target and to output an output signal; 
 a peak hold circuit to hold a peak value of the output signal and to output a hold value; and 
 an impedance calculation circuit to calculate the impedance in the target based on the hold value, 
 wherein the peak value comprises a maximum value of the output signal, 
 the hold value comprises a maximum hold value, and 
 the peak hold circuit comprises: 
 a first current source to output a first current; 
 a first switch supplied with the first current from one end thereof; 
 a first capacitor element, connected to another end of the first switch, the element comprising one end to output the maximum hold value and another end supplied with a first voltage; and 
 a first comparator to turn on the first switch when the output signal is larger than or equal to the maximum hold value and to turn off the first switch when the output signal is less than the maximum hold value. 
 
     
     
       6. The impedance measuring circuit according to  claim 5 ,
 wherein the peak value comprises a minimum value of the output signal, 
 the hold value comprises a minimum hold value, and 
 the peak hold circuit comprises: 
 a second capacitor element comprising one end supplied with the first voltage and another end to output the minimum hold value; 
 a second switch comprising one end connected to the other end of the second capacitor element; 
 a second current source to import a second current from another end of the second switch; and 
 a second comparator to turn on the second switch when the output signal is smaller than or equal to the minimum hold value and to turn off the second switch when the output signal is larger than the minimum hold value. 
 
     
     
       7. An impedance measuring circuit comprising:
 an amplification circuit connected to a target and to amplify a predetermined input signal with a gain corresponding to an impedance in the target and to output an output signal; 
 a peak hold circuit to hold a peak value of the output signal and to output a hold value; and 
 an impedance calculation circuit to calculate the impedance in the target based on the hold value, 
 wherein the peak value comprises a maximum value and a minimum value of the output signal, 
 the hold value comprises a maximum hold value and a minimum hold value, and 
 the impedance calculation circuit calculates the impedance based on a difference between the maximum hold value and the minimum hold value, 
 wherein the peak hold circuit comprises: 
 a timing signal generating circuit to generate a timing signal synchronized with the input signal; 
 a first capacitor unit comprising a first capacitor element and a second capacitor element and to be switched between a peak hold state and a floating state based on the timing signal, to hold the maximum value and the minimum value in the first capacitor element and the second capacitor element in the peak hold state, and to cause the first capacitor element and the second capacitor element to float in the floating state; 
 a second capacitor unit comprising a third capacitor element and a fourth capacitor element and to be switched between the peak hold state and the floating state based on the timing signal, to hold the maximum value and the minimum value in the third capacitor element and the fourth capacitor element in the peak hold state, and to cause the third capacitor element and the fourth capacitor element to float in the floating state; and 
 a differential amplifier, and 
 the timing signal generating circuit causes the first capacitor unit and the second capacitor unit to switch alternately between the peak hold state and the floating state for every predetermined peak hold cycle, and, when an AD conversion command is given, causes the first capacitor element and the second capacitor element or the third capacitor element and the fourth capacitor element which are in the floating state from among the first capacitor unit and the second capacitor unit to be connected to the differential amplifier, and causes the differential amplifier to conduct sample-hold of the held maximum value and the held minimum value as the maximum hold value and the minimum hold value. 
 
     
     
       8. The impedance measuring circuit according to  claim 7 ,
 wherein the peak hold circuit comprises: 
 a third capacitor unit comprising a fifth capacitor element and a sixth capacitor element and to be switched between the peak hold state and the floating state based on the timing signal, to hold the maximum value and the minimum value in the fifth capacitor element and the sixth capacitor element in the peak hold state, and to cause the fifth capacitor element and the sixth capacitor element to float in the floating state; and 
 a fourth capacitor unit comprising a seventh capacitor element and an eighth capacitor element and to be switched between the peak hold state and the floating state based on the timing signal, to hold the maximum value and the minimum value in the seventh capacitor element and the eighth capacitor element in the peak hold state, and to cause the seventh capacitor element and the eighth capacitor element to float in the floating state, and 
 the timing signal generating circuit causes the third capacitor unit and the fourth capacitor unit to switch alternately between the peak hold state and the floating state for every peak hold cycle when the AD conversion command is given and, when the AD conversion command is subsequently given, causes the first capacitor unit and the second capacitor unit to switch alternately between the peak hold state and the floating state for every peak hold cycle, causes the fifth capacitor element and the sixth capacitor element or the seventh capacitor element and the eighth capacitor element which are in the floating state from among the third capacitor unit and the fourth capacitor unit to be connected to the differential amplifier, and causes the differential amplifier to conduct sample-hold of the held maximum value and the held minimum value as the maximum hold value and the minimum hold value. 
 
     
     
       9. The impedance measuring circuit according to  claim 8 ,
 wherein the peak hold circuit comprises a current source circuit to supply a first current when the output signal is larger than or equal to the maximum value and to import a second current when the output signal is smaller than or equal to the minimum value, and 
 the timing signal generating circuit causes the current source circuit to supply the first current to the first, third, fifth or seventh capacitor element which is in the peak hold state from among the first to fourth capacitor units and to import the second current from the second, fourth, sixth or eighth capacitor element which is in the peak hold state from among the first to fourth capacitor units.