Decoupling arrangement

Abstract

In various embodiments, apparatuses and methods are disclosed that may be able to implement a multi-layer, three dimensional routing between a decoupling component and an input port for a SoC or MCM. A three dimensional (3D) structure may provide a defined current return path from the decoupling component to the input port. The current return path may be constrained by design to provide an equal and opposite electromagnetic flux to the input port thereby reducing series inductance between the input port and the decoupling component.

What is claimed is: 
     
       1. An apparatus, comprising:
 a decoupling arrangement to reduce an inductance between a port and a decoupling component, the decoupling arrangement comprising:
 a first current path to electrically couple the port to the decoupling component, the first current path comprising a conductive trace in a first layer of a multi-layer substrate; and 
 a second current path to electrically couple the port to the decoupling component, the second current path comprising a conductive trace in a second layer of the multi-layer substrate, the first and second current paths comprising vertically spaced current paths that substantially cover one another. 
 
 
     
     
       2. The apparatus of  claim 1 , the port to comprise a power supply port. 
     
     
       3. The apparatus of  claim 1 , the decoupling component to comprise a capacitor. 
     
     
       4. The apparatus of  claim 1 , the decoupling component to comprise a plurality of capacitors. 
     
     
       5. The apparatus of  claim 1 , the decoupling arrangement to reduce an inductance between a second port and the decoupling component. 
     
     
       6. The apparatus of  claim 1 , the port to comprise a port of a chip component. 
     
     
       7. The apparatus of  claim 6 , the chip component to comprise a field programmable gate array (FPGA). 
     
     
       8. The apparatus of  claim 6 , the chip component comprised on a printed circuit board (PCB). 
     
     
       9. The apparatus of  claim 8 , the decoupling component comprised on the PCB.