Semiconductor device and method for fabricating the same

Abstract

In one embodiment, the semiconductor device includes at least one active fin protruding from a substrate, a first gate electrode crossing the active fin, and a first impurity region formed on the active fin at a first side of the first gate electrode. At least a portion of the first impurity region is formed in a first epitaxial layer portion on the active fin. A second impurity region is formed on the active fin at a second side of the first gate electrode. The second impurity region has at least a portion not formed in an epitaxial layer.

We claim: 
     
       1. A method of fabricating a semiconductor device, comprising:
 forming a first gate electrode across an active fin projecting from a substrate, the first gate electrode having a first side and a second side; 
 forming an etch stop layer on the active fin at the second side of the first gate electrode; 
 etching the active fin to form a first trench in the active fin at the first side of the first gate electrode; 
 forming an epitaxial layer on the active fin using the first gate electrode and the etch stop layer as masks such that a first epitaxial layer portion fills the first trench; and 
 conducting doping operations to form a first impurity region in a portion of the first epitaxial layer portion and a second impurity region in the active fin at the second side of the first gate electrode. 
 
     
     
       2. The method of  claim 1 , further comprising:
 forming an insulating layer over the substrate; 
 forming first and second contact holes in the insulating layer, the first contact hole exposing a portion of the first impurity region and the second contact hole exposing a portion of the second impurity region; and 
 forming first and second contacts in the first and second contact holes, respectively, such that the first contact is electrically connected to the first impurity region and the second contact is electrically connected to the second impurity region. 
 
     
     
       3. The method of  claim 1 , wherein
 the etch stop layer exposes a first portion of the active fin at a second side of the first gate electrode; 
 the etching forms a second trench in the first portion; 
 the forming an epitaxial layer forms a second epitaxial layer portion in the second trench; and 
 the conducting forms part of the second impurity region in the second epitaxial layer portion. 
 
     
     
       4. The method of  claim 3 , wherein the second epitaxial layer portion is at a proximal end of the second impurity region with respect to the first gate electrode. 
     
     
       5. The method of  claim 3 , wherein the second epitaxial layer portion is at a distal end of the second impurity region with respect to the first gate electrode. 
     
     
       6. The method of  claim 3 , wherein the forming an epitaxial layer forms the first and second epitaxial layer portions such that a top surface of the first epitaxial layer portion and a top surface of the second epitaxial layer portion are both higher than a top surface of the active fin. 
     
     
       7. The method of  claim 1 , wherein the forming an etch stop layer forms the etch stop layer to cover an entirety of a portion of the active fin at which the second impurity region is to be formed. 
     
     
       8. The method of  claim 1 , wherein the second impurity region has a greater width in a longitudinal direction of the active fin than the first impurity region. 
     
     
       9. The method of  claim 1 , wherein the conducting comprising:
 conducting a first ion implantation; 
 forming a mask covering the substrate such that etch stop layer is exposed; and 
 conducting a second ion implantation. 
 
     
     
       10. The method of  claim 1 , further comprising:
 removing the etch stop layer.