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US10026707B2ActiveUtilityPatentIndex 42

Wafer level package and method

Assignee: MICROCHIP TECH INCPriority: Sep 23, 2016Filed: Aug 1, 2017Granted: Jul 17, 2018
Est. expirySep 23, 2036(~10.2 yrs left)· nominal 20-yr term from priority
Inventors:CHU GEORGE
H10W 72/942H10W 72/29H10W 72/952H10W 72/9415H10W 72/9223H10W 72/921H10W 72/923H10W 72/019H10W 72/01953H10W 72/01935H10W 72/01938H10W 70/655H10W 70/69H10W 70/654H10W 70/68H10W 70/65H10W 70/05H10W 72/981H10W 72/983H10W 72/252H10W 72/242H10W 72/222H10W 72/01257H10W 72/01255H10W 72/01235H10W 72/283H10W 42/121H10W 74/47C23C 14/34H10W 74/147C25D 5/022H10W 72/287H10W 90/701H10W 72/072H10W 20/063H01L 2224/05124H01L 2224/0361H01L 2224/13147H01L 2224/02351H01L 2224/03912H01L 23/3192H01L 2224/03464H01L 2224/05583H01L 24/03H01L 2224/05155H01L 23/562H01L 2224/05569H01L 2224/05027H01L 2224/024H01L 21/76885H01L 2224/131H01L 2224/02379H01L 2224/05647H01L 2924/01029H01L 2224/05166H01L 2224/10145H01L 2224/11464H01L 24/11H01L 2224/05582H01L 2224/0345H01L 2224/13083H01L 2224/1146H01L 2924/206H01L 2924/14H01L 2224/05171H01L 2224/05083H01L 2224/10126H01L 2224/1147H01L 2924/07025H01L 2224/0235H01L 2224/0215H01L 2224/13155H01L 2224/0236H01L 23/293H01L 2224/05005H01L 2224/0401H01L 2224/05022H01L 2924/00014H01L 2224/05082H01L 2224/02126H01L 2224/02145H01L 2924/3511H01L 24/05H01L 2224/05008H01L 2924/06H01L 2924/01074H01L 23/49811H01L 2224/05572H01L 2924/014H01L 24/81H01L 2224/11849H01L 2224/02375H01L 24/13H01L 2224/02311H10W 72/20H10W 72/012
42
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Claims

Abstract

A copper pillar bump semiconductor packaging method patterns an organic insulation layer formed under the copper pillar bumps to areas surrounding and in the vicinity of the copper pillar bumps only. The organic insulation layer, typically a thin film polymer layer, acts as a barrier layer for the copper pillar bumps to protect the semiconductor wafer during the copper pillar flip chip bonding process. The copper pillar bump semiconductor packaging method limits the areas where the organic insulation layer is applied to reduce the stress introduced to the semiconductor wafer by the organic insulation layer. In another embodiment, a copper pillar bump semiconductor packaging method patterns an organic insulation layer formed under the copper pillar bumps to areas surrounding the copper pillar bumps and along the path of a redistribution layer without using a large and continuous organic insulation layer.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A method of forming a copper pillar bump semiconductor package, comprising:
 providing a finished semiconductor wafer comprising a semiconductor substrate having a passivation layer formed thereon covering a top surface of the semiconductor substrate and exposing a bond pad; 
 forming a first organic insulation layer on the semiconductor wafer; 
 patterning the first organic insulation layer to cover a first area at an interface of the bond pad and the passivation layer, to cover a second area of a bump pad to be formed, and to form islands of the first organic insulation layer along a path of a redistribution layer to be formed from the bond pad to the bump pad, the first organic insulation layer being removed from the bond pad and from the remaining area of the semiconductor wafer outside the first area, the second area and the islands of first organic insulation layer; 
 forming a first seed metal layer on the first organic insulation layer and the semiconductor wafer; 
 forming the redistribution layer on the semiconductor wafer over the bond pad and the first organic insulation layer, the redistribution layer being formed to include the bump pad being spaced apart from the bond pad and a conductive trace connecting the bond pad to the bump pad, the bump pad being formed over the second area of the first organic insulation layer and the conductive trace being formed over the islands of the first organic insulation layer; 
 removing the first seed metal layer not formed under the redistribution layer; 
 forming a second seed metal layer on the redistribution layer and the semiconductor wafer; 
 forming a copper pillar bump on the second seed metal layer and above the bump pad; 
 removing the second seed metal layer not formed under the copper pillar bump; and 
 reflowing the copper pillar bump. 
 
     
     
       2. The method of  claim 1 , wherein forming the first organic insulation layer on the semiconductor wafer comprises:
 forming the first organic insulation layer on the semiconductor wafer, the first organic insulation layer comprising a thin film polymer material. 
 
     
     
       3. The method of  claim 2 , wherein the first organic insulation layer comprises polyimide (PI) or polybenzoxazole (PBO). 
     
     
       4. The method of  claim 1 , wherein patterning the first organic insulation layer to cover the first area at the interface of the bond pad and the passivation layer comprises:
 patterning the first organic insulation layer to cover the first area at the interface of the bond pad and the passivation layer, the first organic insulation layer overlapping the interface with an overlap width, the first organic insulation layer being removed from the bond pad and from the remaining area of the semiconductor wafer outside the first area, the second area and the islands of first organic insulation layer. 
 
     
     
       5. The method of  claim 4 , wherein patterning the first organic insulation layer to cover the first area at the interface of the bond pad and the passivation layer comprises:
 patterning the first organic insulation layer in a circular shape to cover the first area at the interface of the bond pad and the passivation layer, the first organic insulation layer overlapping the interface with an overlap width, the first organic insulation layer being removed from the bond pad and from the remaining area of the semiconductor wafer outside the first area, the second area and the islands of first organic insulation layer. 
 
     
     
       6. The method of  claim 4 , wherein patterning the first organic insulation layer to cover the area at the interface of the bond pad and the passivation layer comprises:
 patterning the first organic insulation layer in a rectangular shape to cover the first area at the interface of the bond pad and the passivation layer, the first organic insulation layer overlapping the interface with an overlap width, the first organic insulation layer being removed from the bond pad and from the remaining area of the semiconductor wafer outside the first area, the second area and the islands of first organic insulation layer. 
 
     
     
       7. The method of  claim 1 , wherein forming the first organic insulation layer on the semiconductor wafer and patterning the first organic insulation layer comprises:
 forming the first organic insulation layer to cover the entire surface of the semiconductor wafer; and 
 patterning the first organic insulation layer to remove the organic insulation layer from the surface of the semiconductor wafer except at the first area at the interface of the bond pad and the passivation layer, the second area of the bump pad to be formed and the islands of the first organic insulation layer. 
 
     
     
       8. The method of  claim 1 , wherein forming the redistribution layer on the semiconductor wafer comprises:
 patterning the semiconductor wafer to expose areas where the redistribution layer is to be formed; and 
 forming, by plating, a copper layer in the exposed areas as the redistribution layer on the semiconductor wafer. 
 
     
     
       9. The method of  claim 1 , further comprising:
 after removing the first seed metal layer and before forming the second seed metal layer, forming a second organic insulation layer on the semiconductor wafer over the redistribution layer; and 
 patterning the second organic insulation layer to cover a third area over and around the bond pad, to cover a fourth area around the bump pad, and to form islands of the second organic insulation layer along the path of the redistribution layer from the bond pad to the bump pad, the second organic insulation layer being removed from the bump pad and from the remaining area of the semiconductor wafer outside the third area and the fourth area, 
 wherein the second seed metal layer is formed on the semiconductor wafer over the bump pad formed by the redistribution layer and the second organic insulation layer. 
 
     
     
       10. The method of  claim 9 , wherein the islands of the second organic insulation layer are formed offset from the islands of the first organic insulating layer. 
     
     
       11. The method of  claim 9 , wherein forming the second organic insulation layer on the semiconductor wafer over the redistribution layer comprises:
 forming the second organic insulation layer on the semiconductor wafer over the redistribution layer, the second organic insulation layer comprising a thin film polymer material. 
 
     
     
       12. The method of  claim 11 , wherein the second organic insulation layer comprises polyimide (PI) or polybenzoxazole (PBO). 
     
     
       13. The method of  claim 9 , wherein forming the second organic insulation layer on the semiconductor wafer and patterning the second organic insulation layer comprises:
 forming the second organic insulation layer to cover the entire surface of the semiconductor wafer over the redistribution layer; and 
 patterning the second organic insulation layer to remove the second organic insulation layer from the surface of the semiconductor wafer except at the third area over and around the bond pad, the fourth area around the bump pad, and the islands of the second organic insulation layer.

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