Method for synchronously distributing a digital signal over N identical adjacent blocks of an integrated circuit

Abstract

The invention proposes a method for distributing a signal to each block Bj of a series of N adjacent blocks of identical design in an electronic circuit. It proposes, in an identical fashion for each of the N blocks, placing a timing delay circuit MUX-DELj on the path for conveying a signal Sc from the input INcj of the block to an internal electrical node Ndj of the block for this signal Sc; providing for the timing delay circuit to supply N delayed signals corresponding to N different timing delays Δf1, . . . Δfj, . . . ΔfN separated by an increment of elementary duration Δt that corresponds to the elementary delay Δt for transit of a block introduced into a conductive line; and selecting the delayed signal corresponding to the applicable timing delay according to the block in question, by means of an index signal propagated through the N blocks, and which is incremented or decremented on passage through each block.

The invention claimed is: 
     
       1. A method for distributing a digital signal to each of the blocks of an aligned succession of N identical adjacent blocks of an electronic circuit, by means of conductive signal lines transiting the N blocks along the alignment axis of the blocks, the transit through each of the N blocks introducing an elementary delay Δt, wherein the method comprises
 an automatic indexing of the blocks by means of propagation of an index signal through the N blocks, with incrementation or decrementation of an index value of said index signal on passage through each block, said automatic indexing setting a respective index value for each of the N blocks of the succession, 
 a signal timing delay applied to the input of each block, between a conductive line for a signal and an internal electrical node for application of said signal, and the applied timing delay time is selected by means of the index value set for this block, from N different timing delay times separated by an increment of elementary duration Δt that corresponds to the elementary delay Δt for transit of a block introduced into a conductive line, 
 
       and in that this timing delay is implemented by means of one timing delay circuit per block, which is identical for each block, that is connected between the input and the internal node of the block, and that comprises N delay circuits in order to supply the N timing delay times, said delay circuits each being connected between the input of the block and a respective input channel of a multiplexer having N input channels and one output channel, said output channel being connected to the internal node of the block, and said index value set for the block being applied to the multiplexer as an input channel selection input, said method being such that for any j, j an integer from 1 to N, a digital signal transmitted by a respective conductive line and received at the input of the j-th block of the succession after having transited the j−1 previous blocks of the succession, is applied to the internal node of this block with a timing delay that is greater by Δt than the corresponding timing delay in the (j+1)-th block or less by Δt than the corresponding timing delay in the (j−1)-th block. 
     
     
       2. The distribution method of  claim 1 , applied to the distribution of M digital signals, M an integer at least equal to 1, where each of the M digital signals is distributed to a corresponding internal electrical node in each of the N blocks of the succession, wherein the timing delay of each of the M digital signals in each of the N blocks of the succession is provided by M identical timing delay circuits in each of the N blocks, receiving the index signal selecting a delay from N delays. 
     
     
       3. The distribution method of  claim 1 , applied to the distribution of N digital signals by N conductive lines transiting the N blocks of the succession, where each of the N digital signals is applied to an internal electrical node of a single respective block of the succession of N blocks, characterized in that it moreover comprises a routing of the N signals inside each block, which is identical for each block, between N input pads i 1  to i N  and N output pads o 1  to o N  of the block, the routing input and output pads of the same rank being aligned on the N blocks, and the N output pads of a block being connected to the N input pads of the next block, correspondingly, said routing inside each block being such that:
 a first input pad of the block is connected to the input of a timing delay circuit of the block; 
 the other N−1 input pads of the block are connected to the first N−1 output pads of the block such that the input pad having the rank k, where k=2 to N, is connected to the output pad of rank k−1; and 
 the N-th routing output pad of the block is referenced to an internal voltage reference. 
 
     
     
       4. The distribution method of  claim 1 , in which the index signal is incremented by one unit on passage through each block when it is propagated in the same direction as the digital signal(s), or decremented by one unit when it is propagated in the opposite direction. 
     
     
       5. The distribution method of  claim 2 , in which the index signal is incremented by one unit on passage through each block when it is propagated in the same direction as the digital signal(s), or decremented by one unit when it is propagated in the opposite direction. 
     
     
       6. The distribution method of  claim 3 , in which the index signal is incremented by one unit on passage through each block when it is propagated in the same direction as the digital signal(s), or decremented by one unit when it is propagated in the opposite direction. 
     
     
       7. An electronic circuit having at least one aligned succession of N identical adjacent blocks and one or more conductive lines transiting the N blocks along the alignment axis of the blocks, which allow application of at least one digital signal to an input of each of the N blocks of the succession for the purpose of transmitting this signal to a respective internal electrical node of the block, characterized in that each block comprises
 an index signal input for receiving an index signal and propagating it through the N blocks, with incrementation or decrementation of an index value of the index signal on passage through the block, in order to set a respective index value for each of the N blocks of the succession, 
 one signal timing delay circuit per block, which is identical for each block, and connected between the input of the block and the internal electrical node of the block, the timing delay circuit comprising N delay circuits in order to supply a series of N different timing delay times separated by an increment of elementary duration Δt that corresponds to the elementary delay Δt for transit of a block introduced into a conductive line, 
 
       the N delay circuits each being connected between the input of the block and a respective input channel of a multiplexer having N input channels and one output channel, said output channel being connected to the internal node of the block, and said index value set for the block being applied to the multiplexer as an input channel selection input, in order to select a delay from N, 
       such that, for a block of rank j in the succession of blocks, j an integer, equal to 1 to N, a digital signal transmitted by a respective conductive line and received at the input of this block after having transited the j−1 previous blocks of the succession, is applied to the internal node of this block with a delay incremented by Δt in relation to the delay applied in the block of next rank j+1 or decremented by Δt in relation to the delay applied in the block of previous rank j−1. 
     
     
       8. The electronic circuit of  claim 7 , comprising M conductive lines transporting M different digital signals through the N blocks of the succession, which are applied to M internal electrical nodes in each of the N blocks of the succession, through M identical timing delay circuits, and the M timing delay circuits in each of the N blocks receive the same index signal. 
     
     
       9. The electronic circuit of  claim 7 , in which the block receives N different digital signals from which a single signal of rank j needs to be applied to an internal electrical node of the block of rank j, by the timing delay circuit of the block, the block moreover comprising a circuit for routing the N digital signals inside each block, between N input pads i 1  to i N  and N output pads o 1  to o N , of the block, the routing input and output pads of the same rank being aligned on the N blocks, on each of the N output pads on a block being connected to the input pad of the same rank of the next block, the routing circuit being identical in each of the N blocks of the succession and such that:
 a first input pad of the block is connected to the input of a timing delay circuit of the block; 
 the other N−1 input pads of the block are connected to the first N−1 output pads of the block, such that the input pad having the rank k, where k=2 to N, is connected to the output pad of rank k−1; and 
 the N-th routing output pad of the block is referenced to an internal voltage reference. 
 
     
     
       10. The electronic circuit of  claim 7 , in which the N blocks of the succession comprise a circuit for incrementing the index signal, wherein this circuit is an incrementation circuit when the index signal is propagated in the same direction as the digital signal(s), and a decrementation circuit when it is propagated in the opposite direction. 
     
     
       11. The electronic circuit of  claim 8 , in which the N blocks of the succession comprise a circuit for incrementing the index signal, wherein this circuit is an incrementation circuit when the index signal is propagated in the same direction as the digital signal(s), and a decrementation circuit when it is propagated in the opposite direction. 
     
     
       12. The electronic circuit of  claim 9 , in which the N blocks of the succession comprise a circuit for incrementing the index signal, wherein this circuit is an incrementation circuit when the index signal is propagated in the same direction as the digital signal(s), and a decrementation circuit when it is propagated in the opposite direction.