Power MOSFET with a deep source contact

Abstract

A power MOSFET IC device including an array of MOSFET cells formed in a semiconductor substrate. The array of MOSFET cells comprises an interior region of interior MOSFET cells and an outer edge region of peripheral MOSFET cells, each interior MOSFET cell of the interior region of the array comprising a pair of interior MOSFET devices coupled to each other at a common drain contact. In an example embodiment, each interior MOSFET device includes a source contact (SCT) trench extended into a substrate contact region of the semiconductor substrate. The SCT trench is provided with a length less than a linear portion of a polysilicon gate of the interior MOSFET device, wherein the SCT trench is aligned to the polysilicon gate having a curvilinear layout geometry.

What is claimed is: 
     
       1. An integrated circuit (IC), comprising:
 a semiconductor substrate having a top surface and a bottom surface; and 
 at least one metal-oxide-semiconductor field effect transistor (MOSFET) cell formed in the semiconductor substrate, the MOSFET cell comprising a pair of MOSFET devices coupled to each other at a common drain contact, wherein at least one MOSFET device includes a source contact (SCT) trench extended into a substrate contact region in the semiconductor substrate proximate to the bottom surface, the SCT trench having a length along the top surface less than a linear portion of a polysilicon gate of the at least one MOSFET device, the SCT trench aligned to a complementary contour of the polysilicon gate having a curvilinear layout geometry. 
 
     
     
       2. The IC as recited in  claim 1 , further comprising an array of MOSFET cells, wherein a peripheral cell of the array comprises a peripheral MOSFET device and an inactive circuit portion formed in the semiconductor substrate. 
     
     
       3. The IC as recited in  claim 2 , wherein the peripheral MOSFET device includes a second polysilicon gate having a second length along the top surface, and the second length shorter than the length of the polysilicon gate of the at least one MOSFET device. 
     
     
       4. The IC as recited in  claim 2 , wherein the peripheral MOSFET device includes a second polysilicon gate having a second length along the top surface, and the second length same as the length of the polysilicon gate of the at least one MOSFET device. 
     
     
       5. The IC as recited in  claim 2 , further comprising a ground tab coupled to a field plate of the peripheral MOSFET device. 
     
     
       6. The IC as recited in  claim 5 , wherein the field plate comprises at least one refractory metal material layer formed of a material selected from the group of titanium, titanium nitride (Ti/TiN), tungsten and Ti-tungsten (Ti—W). 
     
     
       7. The IC as recited in  claim 1 , wherein the SCT trench has an aspect ratio of at least 2:1. 
     
     
       8. The IC as recited in  claim 1 , wherein the SCT trench is filled with a metallic plug comprising a refractory metal or platinum-group metal (PGM) filler for forming an electrical contact with a source terminal of the at least one MOSFET device. 
     
     
       9. A laterally diffused metal-oxide-semiconductor transistor (LDMOS) device, comprising:
 a semiconductor substrate having a top surface and a bottom surface, the semiconductor substrate having a doped layer positioned adjacent to the top surface and having an upper surface; 
 source and drain regions of a first conductivity type positioned in the doped layer proximate the upper surface of the doped layer, the source and drain regions being spaced from one another and separated by a channel region of a second conductivity type formed in the doped layer, the channel region having a portion extending under the source region, wherein the drain region comprises a lightly doped drain (LDD) region formed adjacent to the channel region; 
 a doped drain contact region spaced from the channel region by the lightly doped drain region; 
 a conductive gate having an upper surface and sidewall surfaces, the conductive gate formed over a gate dielectric layer formed over the channel region, the conductive gate at least partially overlapping the source and drain regions; 
 a conductive path connecting the source region and the semiconductor substrate via a conductor disposed in a source contact (SCT) trench formed in the doped layer and extended into a substrate contact region in the semiconductor substrate, the SCT trench having a length along the top surface less than a linear portion of the conductive gate, the SCT trench aligned to a complementary contour of the conductive gate having a curvilinear geometry; 
 a first insulating layer over the upper surface and sidewall surfaces of the conductive gate; 
 a field plate layered over the lightly doped drain region and at least a portion of the first insulating layer, wherein the field plate is connected to the source region; 
 a second insulating layer over the layer of field plate, the first insulating layer and the trench; and 
 a drain electrode electrically coupled to the drain contact region. 
 
     
     
       10. The LDMOS device as recited in  claim 9 , wherein the SCT trench has an aspect ratio of at least 2:1. 
     
     
       11. The LDMOS device as recited in  claim 9 , wherein the field plate comprises at least one refractory metal material layer formed of a material selected from the group of titanium, titanium nitride (Ti/TiN), tungsten and Ti-tungsten (Ti—W). 
     
     
       12. The LDMOS device as recited in  claim 9 , wherein the SCT trench is filled with a metallic plug forming the conductor comprising a refractory metal or platinum-group metal (PGM) filler.