Forming self-aligned contacts on pillar structures

Abstract

A method of forming a semiconductor structure includes forming two or more pillar structures over a top surface of a substrate. The method also includes forming two or more contacts to the two or more pillar structures. The method further includes forming an insulator between the two or more pillar structures and the two or more contacts. The two or more contacts are self-aligned to the two or more pillar structures by forming the insulator via conformal deposition and etching the insulator selective to a spin-on material formed over the insulator between the two or more pillar structures.

What is claimed is: 
     
       1. A method of forming a semiconductor structure, comprising:
 forming two or more pillar structures over a top surface of a substrate; 
 forming two or more contacts to the two or more pillar structures; and 
 forming an insulator between the two or more pillar structures and the two or more contacts; 
 wherein the two or more contacts are self-aligned to the two or more pillar structures by forming the insulator via conformal deposition and etching the insulator selective to a spin-on material formed over the insulator between the two or more pillar structures, 
 wherein the two or more contacts comprise a first contact of a first material contacting a first one of the two or more pillar structures and a second contact of a second material different than the first material contacting a second one of the two or more pillar structures. 
 
     
     
       2. The method of  claim 1 , further comprising:
 forming an etch stop layer over the two or more pillar structures and the top surface of the substrate; 
 forming the insulator over the etch stop layer such that a top surface of portions of the insulator formed over tops of the two or more pillar structures are higher than the top surface of the insulator formed between the two or more pillar structures; 
 forming the spin-on material over the top surface of the insulator between the two or more pillar structures; 
 forming two or more contact trenches by etching the insulator and the etch stop layer formed over tops of the two or more pillar structures selective to the spin-on material; 
 depositing contact material in the two or more contact trenches; and 
 planarizing to remove the spin-on material. 
 
     
     
       3. The method of  claim 1 , wherein the insulator and the spin-on material have different etch rates. 
     
     
       4. The method of  claim 3 , wherein the insulator comprises an oxide and the spin-on material comprises one of an organic planarization layer and a flowable oxide. 
     
     
       5. The method of  claim 1 , wherein a given one of the two or more pillar structures comprises a pillar and a capping layer formed over the pillar. 
     
     
       6. The method of  claim 5 , wherein the capping layer comprises tantalum nitride (TaN). 
     
     
       7. The method of  claim 5 , wherein the pillar comprises a magnetic tunnel junction (MTJ) stack for a magnetic random access memory (MRAM) cell. 
     
     
       8. The method of  claim 7 , wherein the MTJ stack comprises an insulating layer formed between a first ferromagnetic layer and a second ferromagnetic layer. 
     
     
       9. The method of  claim 8 , wherein the insulating layer comprises magnesium oxide (MgO) and at least one of the first ferromagnetic layer and the second ferromagnetic layer comprises at least one of a cobalt-nickel (Co—Ni) alloy and a cobalt-iron-boron (Co—Fe—B) alloy. 
     
     
       10. The method of  claim 5 , wherein the pillar comprises a metal-insulator-metal (MIM) capacitor. 
     
     
       11. The method of  claim 5 , wherein the pillar comprises a resistor of at least one of a phase change memory structure and a resistive random access memory (ReRAM) structure. 
     
     
       12. The method of  claim 1 , further comprising forming one or more metal layers in the substrate beneath at least a portion of at least one of the two or more pillar structures. 
     
     
       13. The method of  claim 1 , wherein forming the two or more contacts comprises depositing a liner material in two or more contact trenches formed in the insulator and depositing contact material over the liner material. 
     
     
       14. A method of forming a semiconductor structure, comprising:
 forming two or more pillar structures over a top surface of a substrate; 
 forming two or more contacts to the two or more pillar structures; and 
 forming an insulator between the two or more pillar structures and the two or more contacts; 
 wherein the two or more contacts are self-aligned to the two or more pillar structures by forming the insulator via conformal deposition and etching the insulator selective to a spin-on material formed over the insulator between the two or more pillar structures, 
 wherein a first one of the two or more pillar structures has a first height relative to the top surface of the substrate and a second one of the two or more pillar structures has a second height different than the first height relative to the top surface of the substrate. 
 
     
     
       15. A method of forming a semiconductor structure, comprising:
 forming two or more pillar structures over a top surface of a substrate; 
 forming two or more contacts to the two or more pillar structures; and 
 forming an insulator between the two or more pillar structures and the two or more contacts; 
 wherein the two or more contacts are self-aligned to the two or more pillar structures by forming the insulator via conformal deposition and etching the insulator selective to a spin-on material formed over the insulator between the two or more pillar structures, 
 wherein a first one of the two or more pillar structures has a first width in a direction parallel to the top surface of the substrate and a second one of the two or more pillar structures has a second width in the direction parallel to the top surface of the substrate, the second width being different than the first width.