Data transmission method and media access controller

Abstract

Embodiments provide a data transmission method, including: receiving, by a receiving circuit in a media access controller, N packets; generating, by a distributing circuit, a first data block and a second data block, where the first data block includes a first set, and the second data block includes a second set; distributing the first data block to a first circuit, and distributing the second data block to a second circuit; converting, by the first circuit, the first data block into first data, and converting, by the second circuit, the second data block into second data; and sending, by the first circuit, the first data through a first channel, and sending, by the second circuit, the second data through a second channel. In addition, another method and a corresponding media access controller are further provided. The foregoing technical solution helps reduce circuit resources occupied by an Ethernet interface.

What is claimed is: 
     
       1. A data transmission method, comprising:
 receiving, by a receiving circuit in a media access controller (MAC), N packets, wherein the N packets sequentially arrive at the MAC in a time sequence from the first packet to the N th  packet, and N is a positive integer greater than 1; 
 generating, by a distributing circuit in the MAC, a first data block and a second data block, wherein the first data block comprises a first set, the first set comprises the first packet to the M th  packet, and the first packet to the M th  packet are sequentially carried in the first data block in a location sequence from the first packet to the M th  packet; the second data block comprises a second set, the second set comprises the (M+1) th  packet to the N th  packet, and the (M+1) th  packet to the N th  packet are sequentially carried in the second data block in a location sequence from the (M+1) th  packet to the N th  packet; the first data block comprises a first identifier, the second data block comprises a second identifier, the first identifier is used to indicate a time sequence that the first set arrives at the MAC, the second identifier is used to indicate a time sequence that the second set arrives at the MAC, M is a positive integer, and M is less than N; 
 distributing, by the distributing circuit, the first data block to a first circuit in the MAC, and distributing, by the distributing circuit, the second data block to a second circuit in the MAC; 
 converting, by the first circuit, the first data block into first data, and converting, by the second circuit, the second data block into second data; and 
 sending, by the first circuit, the first data through a first channel, and sending, by the second circuit, the second data through a second channel. 
 
     
     
       2. The method according to  claim 1 , wherein:
 the first identifier is carried in an Ethernet interpacket gap IPG, a packet header of a packet, or a payload of a packet; or 
 the second identifier is carried in an Ethernet interpacket gap IPG, a packet header of a packet, or a payload of a packet. 
 
     
     
       3. The method according to  claim 1 , wherein:
 before the distributing, by the distributing circuit, the first data block to a first circuit in the MAC, the method further comprises: 
 comparing, by a comparing circuit in the MAC, a length of a queue in a transmit buffer of the first circuit with a length of a queue in a transmit buffer of the second circuit; and 
 determining, by the comparing circuit, that the length of the queue in the transmit buffer of the first circuit is less than or equal to the length of the queue in the transmit buffer of the second circuit; and 
 the distributing, by the distributing circuit, the first data block to a first circuit in the MAC specifically comprises: 
 distributing, by the distributing circuit, the first data block to the first circuit in the MAC based on determining by the comparing circuit that the length of the queue in the transmit buffer of the first circuit is less than or equal to the length of the queue in the transmit buffer of the second circuit. 
 
     
     
       4. The method according to  claim 3 , wherein:
 after the distributing, by the distributing circuit, the first data block to a first circuit in the MAC, and before the distributing, by the distributing circuit, the second data block to a second circuit in the MAC, the method further comprises: 
 comparing, by the comparing circuit, the length of the queue in the transmit buffer of the first circuit with the length of the queue in the transmit buffer of the second circuit; and 
 determining, by the comparing circuit, that the length of the queue in the transmit buffer of the second circuit is less than or equal to the length of the queue in the transmit buffer of the first circuit; and 
 the distributing, by the distributing circuit, the second data block to a second circuit in the MAC specifically comprises: 
 distributing, by the distributing circuit, the second data block to the second circuit in the MAC based on determining by the comparing circuit that the length of the queue in the transmit buffer of the second circuit is less than or equal to the length of the queue in the transmit buffer of the first circuit. 
 
     
     
       5. The method according to  claim 1 , wherein:
 a difference between a maximum length of the first data block and a minimum length of the first data block is greater than or equal to a maximum length of a packet that can be received by the MAC; or 
 a difference between a maximum length of the second data block and a minimum length of the second data block is greater than or equal to a maximum length of a packet that can be received by the MAC. 
 
     
     
       6. A data transmission method, comprising:
 receiving, by a receiving circuit in a media access controller (MAC), first data through a first channel, and receiving, by the receiving circuit, second data through a second channel; 
 sending, by the receiving circuit, the first data to a first circuit in the MAC, and sending, by the receiving circuit, the second data to a second circuit in the MAC; 
 converting, by the first circuit, the first data into a first data block, and converting, by the second circuit, the second data into a second data block, wherein the first data block comprises a first set, the first set comprises the first packet to the M th  packet, and the first packet to the M th  packet are sequentially carried in the first data block in a location sequence from the first packet to the M th  packet; the second data block comprises a second set, the second set comprises the (M+1) th  packet to the N th  packet, and the (M+1) th  packet to the N th  packet are sequentially carried in the second data block in a location sequence from the (M+1) th  packet to the N th  packet; the first data block comprises a first identifier, the second data block comprises a second identifier, the first identifier is used to indicate a time sequence that a peer MAC generates the first data block, the second identifier is used to indicate a time sequence that the peer MAC generates the second data block, M is a positive integer, M is less than N, and N is a positive integer greater than 1; 
 generating, by the first circuit, the first packet to the M th  packet according to the first data block, and generating, by the second circuit, the (M+1) th  packet to the N th  packet according to the second data block; 
 sending, by the first circuit, the first packet to the M th  packet to an aggregating circuit in the MAC; 
 sending, by the second circuit, the (M+1) th  packet to the N th  packet to the aggregating circuit; and 
 sequentially sending, by the aggregating circuit, the N packets in a time sequence from the first packet to the N th  packet. 
 
     
     
       7. The method according to  claim 6 , wherein:
 the first identifier is carried in an Ethernet interpacket gap IPG, a packet header of a packet, or a payload of a packet; or 
 the second identifier is carried in an Ethernet interpacket gap IPG, a packet header of a packet, or a payload of a packet. 
 
     
     
       8. The method according to  claim 6 , wherein:
 a difference between a maximum length of the first data block and a minimum length of the first data block is greater than or equal to a maximum length of a packet that can be generated by the MAC; or 
 a difference between a maximum length of the second data block and a minimum length of the second data block is greater than or equal to a maximum length of a packet that can be generated by the MAC. 
 
     
     
       9. The method according to  claim 6 , wherein:
 after the generating, by the first circuit, the first packet to the M th  packet according to the first data block, and before the sending, by the first circuit, the first packet to the M th  packet to an aggregating circuit in the MAC, the method further comprises: 
 searching, by a searching circuit in the MAC, a look-up table for an entry that matches information in a packet header of at least one packet of the first packet to the M th  packet, to determine a first outbound interface that is used to forward the at least one packet, wherein the entry comprises the information and an identifier of the first outbound interface, the first outbound interface is an outbound interface of a network device, and the MAC is a component of the network device; and 
 the sending, by the first circuit, the first packet to the M th  packet to an aggregating circuit in the MAC specifically comprises: 
 sending, by the first circuit, the at least one packet and the identifier of the first outbound interface to the aggregating circuit. 
 
     
     
       10. The method according to  claim 6 , wherein:
 after the sending, by the first circuit, the first packet to the M th  packet to an aggregating circuit in the MAC, the method further comprises: 
 searching, by a searching circuit in the aggregating circuit, a look-up table for an entry that matches information in a packet header of at least one packet of the first packet to the M th  packet, to determine a first outbound interface that is used to forward the at least one packet, wherein the entry comprises the information and an identifier of the first outbound interface, the first outbound interface is an outbound interface of a network device, and the MAC is a component of the network device; and 
 the sending, by the aggregating circuit, the N packets specifically comprises: 
 sending, by the aggregating circuit, the at least one packet to the first outbound interface. 
 
     
     
       11. A media access controller (MAC), comprising a receiving circuit, a distributing circuit, a first circuit, and a second circuit; wherein:
 the receiving circuit is configured to receive N packets, wherein the N packets sequentially arrive at the MAC in a time sequence from the first packet to the N th  packet, and N is a positive integer greater than 1; 
 the distributing circuit is configured to generate a first data block and a second data block, wherein the first data block comprises a first set, the first set comprises the first packet to the M th  packet, and the first packet to the M th  packet are sequentially carried in the first data block in a location sequence from the first packet to the M th  packet; the second data block comprises a second set, the second set comprises the (M+1) th  packet to the N th  packet, and the (M+1) th  packet to the N th  packet are sequentially carried in the second data block in a location sequence from the (M+1) th  packet to the N th  packet; the first data block comprises a first identifier, the second data block comprises a second identifier, the first identifier is used to indicate a time sequence that the first set arrives at the MAC, the second identifier is used to indicate a time sequence that the second set arrives at the MAC, M is a positive integer, and M is less than N; 
 the distributing circuit is further configured to distribute the first data block to the first circuit and distribute the second data block to the second circuit; 
 the first circuit is configured to convert the first data block into first data; 
 the second circuit is configured to convert the second data block into second data; 
 the first circuit is further configured to send the first data through a first channel; and 
 the second circuit is further configured to send the second data through a second channel. 
 
     
     
       12. The MAC according to  claim 11 , wherein:
 the first identifier is carried in an Ethernet interpacket gap IPG, a packet header of a packet, or a payload of a packet; or 
 the second identifier is carried in an Ethernet interpacket gap IPG, a packet header of a packet, or a payload of a packet. 
 
     
     
       13. The MAC according to  claim 11 , wherein the MAC further comprises a comparing circuit, wherein:
 the comparing circuit is configured to: before the distributing circuit distributes the first data block to the first circuit in the MAC, compare a length of a queue in a transmit buffer of the first circuit with a length of a queue in a transmit buffer of the second circuit; and determine that the length of the queue in the transmit buffer of the first circuit is less than or equal to the length of the queue in the transmit buffer of the second circuit; and 
 the distributing circuit is specifically configured to distribute the first data block to the first circuit in the MAC based on determining by the comparing circuit that the length of the queue in the transmit buffer of the first circuit is less than or equal to the length of the queue in the transmit buffer of the second circuit. 
 
     
     
       14. The MAC according to  claim 13 , wherein:
 the comparing circuit is further configured to: after the distributing circuit distributes the first data block to the first circuit in the MAC, and before the distributing circuit distributes the second data block to the second circuit in the MAC, compare the length of the queue in the transmit buffer of the first circuit with the length of the queue in the transmit buffer of the second circuit; and determine that the length of the queue in the transmit buffer of the second circuit is less than or equal to the length of the queue in the transmit buffer of the first circuit; and 
 the distributing circuit is specifically configured to distribute the second data block to the second circuit in the MAC based on determining by the comparing circuit that the length of the queue in the transmit buffer of the second circuit is less than or equal to the length of the queue in the transmit buffer of the first circuit. 
 
     
     
       15. The MAC according to  claim 11 , wherein:
 a difference between a maximum length of the first data block and a minimum length of the first data block is greater than or equal to a maximum length of a packet that can be received by the MAC; or 
 a difference between a maximum length of the second data block and a minimum length of the second data block is greater than or equal to a maximum length of a packet that can be received by the MAC. 
 
     
     
       16. A media access controller (MAC), comprising a receiving circuit, a first circuit, a second circuit, and an aggregating circuit; wherein:
 the receiving circuit is configured to receive first data through a first channel and receive second data through a second channel; 
 the receiving circuit is further configured to send the first data to the first circuit and send the second data to the second circuit; 
 the first circuit is configured to convert the first data into a first data block, wherein the first data block comprises a first set, the first set comprises the first packet to the M th  packet, and the first packet to the M th  packet are sequentially carried in the first data block in a location sequence from the first packet to the M th  packet; the first data block comprises a first identifier, and the first identifier is used to indicate a time sequence that a peer MAC generates the first data block; 
 the second circuit is configured to convert the second data into a second data block, wherein the second data block comprises a second set, the second set comprises the (M+1) th  packet to the N th  packet, and the (M+1) th  packet to the N th  packet are sequentially carried in the second data block in a location sequence from the (M+1) th  packet to the N th  packet; the second data block comprises a second identifier, and the second identifier is used to indicate a time sequence that the peer MAC generates the second data block, M is a positive integer, M is less than N, and N is a positive integer greater than 1; 
 the first circuit is further configured to generate the first packet to the M th  packet according to the first data block; 
 the second circuit is further configured to generate the (M+1) th  packet to the N th  packet according to the second data block; 
 the first circuit is further configured to send the first packet to the M th  packet to the aggregating circuit; 
 the second circuit is further configured to send the (M+1) th  packet to the N th  packet to the aggregating circuit; and 
 the aggregating circuit is configured to sequentially send the N packets in a time sequence from the first packet to the N th  packet. 
 
     
     
       17. The MAC according to  claim 16 , wherein:
 the first identifier is carried in an Ethernet interpacket gap IPG, a packet header of a packet, or a payload of a packet; or 
 the second identifier is carried in an Ethernet interpacket gap IPG, a packet header of a packet, or a payload of a packet. 
 
     
     
       18. The MAC according to  claim 16 , wherein:
 a difference between a maximum length of the first data block and a minimum length of the first data block is greater than or equal to a maximum length of a packet that can be generated by the MAC; or 
 a difference between a maximum length of the second data block and a minimum length of the second data block is greater than or equal to a maximum length of a packet that can be generated by the MAC. 
 
     
     
       19. The MAC according to  claim 16 , wherein the MAC further comprises a searching circuit, wherein:
 the searching circuit is configured to: after the first circuit generates the first packet to the M th  packet according to the first data block, and before the first circuit sends the first packet to the M th  packet to the aggregating circuit, search a look-up table for an entry that matches information in a packet header of at least one packet of the first packet to the M th  packet, to determine a first outbound interface that is used to forward the at least one packet, wherein the entry comprises the information and an identifier of the first outbound interface, the first outbound interface is an outbound interface of a network device, and the MAC is a component of the network device; and 
 the first circuit is specifically configured to send the at least one packet and the identifier of the first outbound interface to the aggregating circuit. 
 
     
     
       20. The MAC according to  claim 16 , wherein the aggregating circuit further comprises a searching circuit, wherein
 the searching circuit is configured to: after the first circuit sends the first packet to the M th  packet to the aggregating circuit, search a look-up table for an entry that matches information in a packet header of at least one packet of the first packet to the M th  packet, to determine a first outbound interface that is used to forward the at least one packet, wherein the entry comprises the information and an identifier of the first outbound interface, the first outbound interface is an outbound interface of a network device, and the MAC is a component of the network device; and 
 the aggregating circuit is specifically configured to send the at least one packet to the first outbound interface.